[PATCH 1/2] fix-gen9-sync
Chris Wilson
chris at chris-wilson.co.uk
Sun May 3 07:39:02 UTC 2020
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d4ef344657b0..92ce55aa2998 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4656,12 +4656,29 @@ gen8_emit_fini_breadcrumb_footer(struct i915_request *request,
return gen8_emit_wa_tail(request, cs);
}
+static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
+{
+ u64 addr = i915_request_active_timeline(request)->hwsp_offset;
+
+ /* Serialising flush... */
+ *cs++ = (MI_FLUSH_DW + 1) |
+ MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+ *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
+ *cs++ = 0;
+ *cs++ = 0;
+
+ /* But it did not serialise the write with earlier MI_STORE_DWORD_IMM */
+ *cs++ = MI_STORE_DWORD_IMM_GEN4;
+ *cs++ = lower_32_bits(addr);
+ *cs++ = upper_32_bits(addr);
+ *cs++ = request->fence.seqno;
+
+ return cs;
+}
+
static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
{
- cs = gen8_emit_ggtt_write(cs,
- request->fence.seqno,
- i915_request_active_timeline(request)->hwsp_offset,
- 0);
+ cs = emit_xcs_breadcrumb(request, cs);
return gen8_emit_fini_breadcrumb_footer(request, cs);
}
@@ -4751,10 +4768,7 @@ gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
static u32 *gen12_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
{
- cs = gen8_emit_ggtt_write(cs,
- request->fence.seqno,
- i915_request_active_timeline(request)->hwsp_offset,
- 0);
+ cs = emit_xcs_breadcrumb(request, cs);
return gen12_emit_fini_breadcrumb_footer(request, cs);
}
--
2.20.1
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