[PATCH 5/5] ggtt-readl

[Chris Wilson]

---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 66165b10256e..770f2cb1fdff 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -137,6 +137,7 @@ static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
 	 * Note that as an uncached mmio write, this will flush the
 	 * WCB of the writes into the GGTT before it triggers the invalidate.
 	 */
+	wmb();
 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 }
 
@@ -182,6 +183,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
 		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
 
 	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
+	readl(pte);
 
 	ggtt->invalidate(ggtt);
 }
@@ -214,6 +216,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	/* Fill the allocated but "unused" space beyond the end of the buffer */
 	while (gte < end)
 		gen8_set_pte(gte++, vm->scratch[0].encode);
+	readl(end - 1);
 
 	/*
 	 * We want to flush the TLBs only after we're certain all the PTE
-- 
2.20.1