[PATCH 5/5] DEBUG: drm/i915: HOBL debug info

[José Roberto de Souza]

Just for trybot testing.

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c             | 2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c              | 5 +++++
 drivers/gpu/drm/i915/display/intel_dp.c               | 2 ++
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +++++
 4 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index d1e9b1b5ce3f..828d09883470 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -725,6 +725,8 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv,
 
 	if (bdb->version >= 232)
 		dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type);
+
+	drm_dbg_kms(&dev_priv->drm, "power->hobl=0x%x dev_priv->vbt.edp.hobl=0x%x panel_type=0x%x | enabling it anyways for debug\n", power->hobl, dev_priv->vbt.edp.hobl, panel_type);
 	dev_priv->vbt.edp.hobl = true;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5554d3ec5144..e92c0d8af91a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2337,6 +2337,8 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
 	u32 n_entries, val;
 	int ln;
 
+	drm_dbg_kms(&dev_priv->drm, "icl_ddi_combo_vswing_program() phy%c level=%i rate=%i", phy_name(phy), level, rate);
+
 	ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type,
 						    rate, level, &n_entries);
 	if (ddi_translations)
@@ -2708,9 +2710,12 @@ static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
 static void
 tgl_set_signal_levels(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
+	drm_dbg_kms(&dev_priv->drm, "tgl_set_signal_levels()\n");
+
 	tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
 				level, encoder->type);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7223367171d1..d6db27def0a9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5517,6 +5517,7 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 
 void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct drm_dp_phy_test_params *data =
 		&intel_dp->compliance.test_data.phytest;
 	u8 link_status[DP_LINK_STATUS_SIZE];
@@ -5531,6 +5532,7 @@ void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 
 	intel_dp_autotest_phy_ddi_disable(intel_dp);
 
+	drm_dbg_kms(&dev_priv->drm, "intel_dp_process_phy_request()\n");
 	intel_dp_set_signal_levels(intel_dp);
 
 	intel_dp_phy_pattern_update(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index db078780542f..bba37d9327df 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -111,6 +111,9 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
 	if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl)
 		intel_dp->try_hobl = true;
 
+	drm_dbg_kms(&dev_priv->drm, "intel_dp_reset_link_train() intel_dp->hobl_en=0x%x dp_train_pat=0x%x\n",
+		    intel_dp->try_hobl, dp_train_pat);
+
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 	intel_dp_set_signal_levels(intel_dp);
 	return intel_dp_set_link_train(intel_dp, dp_train_pat);
@@ -119,8 +122,10 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat)
 static bool
 intel_dp_update_link_train(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	int ret;
 
+	drm_dbg_kms(&dev_priv->drm, "intel_dp_update_link_train()\n");
 	intel_dp_set_signal_levels(intel_dp);
 
 	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-- 
2.26.2