[PATCH 08/14] drm/i915: Support inter-engine semaphores on gen6/7

[Chris Wilson]

Should we gain per-client timelines, we can then utilise the separate
HWSP in order to use MI_SEMAPHORE_MBOX with the unique GGTT addresses
required for synchronising between clients across different engines.
Teach the emit_semaphore_wait about MI_SEMAPHORE_MBOX for the older
generations.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_request.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index c5d7220de529..bab4c2cd4540 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1040,17 +1040,26 @@ __emit_semaphore_wait(struct i915_request *to,
 	 * (post-wrap) values than they were expecting (and so wait
 	 * forever).
 	 */
-	*cs++ = (MI_SEMAPHORE_WAIT |
-		 MI_SEMAPHORE_GLOBAL_GTT |
-		 MI_SEMAPHORE_POLL |
-		 MI_SEMAPHORE_SAD_GTE_SDD) +
-		has_token;
-	*cs++ = seqno;
-	*cs++ = hwsp_offset;
-	*cs++ = 0;
-	if (has_token) {
+	if (INTEL_GEN(to->i915) >= 8) {
+		*cs++ = (MI_SEMAPHORE_WAIT |
+			 MI_SEMAPHORE_GLOBAL_GTT |
+			 MI_SEMAPHORE_POLL |
+			 MI_SEMAPHORE_SAD_GTE_SDD) +
+			has_token;
+		*cs++ = seqno;
+		*cs++ = hwsp_offset;
+		*cs++ = 0;
+		if (has_token) {
+			*cs++ = 0;
+			*cs++ = MI_NOOP;
+		}
+	} else {
+		*cs++ = (MI_SEMAPHORE_MBOX |
+			 MI_SEMAPHORE_GLOBAL_GTT |
+			 MI_SEMAPHORE_COMPARE);
+		*cs++ = seqno - 1; /* COMPARE is a strict greater-than */
+		*cs++ = hwsp_offset;
 		*cs++ = 0;
-		*cs++ = MI_NOOP;
 	}
 
 	intel_ring_advance(to, cs);
-- 
2.20.1