[RFC] consolidated wa table
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Fri Nov 6 17:11:32 UTC 2020
From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 282 ++++++++++-
.../gpu/drm/i915/gt/intel_workarounds_table.h | 471 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +-
4 files changed, 755 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_workarounds_table.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..d153af5c1fce 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -284,6 +284,7 @@ obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
# exclude some broken headers from the test coverage
no-header-test := \
display/intel_vbt_defs.h \
+ gt/intel_workarounds_table.h \
gvt/execlist.h \
gvt/fb_decoder.h \
gvt/gtt.h \
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fed9503a7c4e..6e718f02fc36 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1726,6 +1726,249 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
i915_mmio_reg_offset(RING_NOPID(base)));
}
+#define wa_or(reg__, set__) \
+ .wa = { .reg = (reg__), .clr = (set__), .set = (set__), .read = (set__) }
+
+#define wa_masked_or(reg__, mask__, set__) \
+ .wa = { .reg = (reg__), .clr = (mask__), .set = (set__), .read = (mask__) }
+
+#define wa_set(reg__, set__) \
+ .wa = { .reg = (reg__), .clr = (~0), .set = (set__), .read = (~0) }
+
+#define wa_en(reg__, val__) \
+ .wa = { .reg = (reg__), .clr = 0, .set = __MASKED_FIELD((val__), (val__)), .read = (val__) }
+
+#define wa_dis(reg__, val__) \
+ .wa = { .reg = (reg__), .clr = 0, .set = __MASKED_FIELD((val__), 0), .read = (val__) }
+
+struct i915_wa_rule {
+#define I915_WA_PLATFORM (1)
+#define I915_WA_GENMASK (2)
+#define I915_WA_ENGINE_CLASS (3)
+ u8 type;
+#define I915_WA_REVID BIT(0)
+#define I915_WA_GTREVID BIT(1)
+#define I915_WA_SUBPLATFORM BIT(2)
+ u8 flags;
+ union {
+ struct {
+ u8 platform;
+ u8 subplatform;
+ u8 start;
+ u8 end;
+ };
+ struct {
+ u32 class_mask;
+ };
+ struct {
+ u16 genmask;
+ };
+ };
+};
+
+struct i915_wa_ng {
+ const char *name;
+#define I915_WA_ENGINE (1)
+ u8 type;
+#define I915_WA_SKIP_VERIFY BIT(0)
+#define I915_WA_MMIO_BASE BIT(1)
+ u8 flags;
+ struct i915_wa wa;
+ const struct i915_wa_rule *rules;
+};
+
+#define wa_engine \
+ .type = I915_WA_ENGINE
+
+#define wa_rules_start .rules = (struct i915_wa_rule []){
+#define wa_rules_end { }, }
+
+#define wa_rule_engine_class(class) \
+ { .type = I915_WA_ENGINE_CLASS, .class_mask = BIT(class) }
+
+#define wa_rule_not_engine_class(class) \
+ { .type = I915_WA_ENGINE_CLASS, .class_mask = ~(u32)BIT(class) }
+
+#define wa_rule_gen(g) \
+ { .type = I915_WA_GENMASK, .genmask = INTEL_GEN_MASK((g), (g)) }
+
+#define wa_rule_gen_range(s, e) \
+ { .type = I915_WA_GENMASK, .genmask = INTEL_GEN_MASK((s), (e)) }
+
+#define wa_rule_platform(p) \
+ { .type = I915_WA_PLATFORM, \
+ .platform = (p), \
+ }
+
+#define wa_rule_platform_revid(p, s, e) \
+ { .type = I915_WA_PLATFORM, \
+ .flags = I915_WA_REVID, \
+ .platform = (p), \
+ .start = (s), \
+ .end = (e) \
+ }
+
+#define wa_rule_platform_gtrevid(p, s, e) \
+ { .type = I915_WA_PLATFORM, \
+ .flags = I915_WA_GTREVID, \
+ .platform = (p), \
+ .start = (s), \
+ .end = (e) \
+ }
+
+#define wa_rule_subplatform_revid(p, sp, s, e) \
+ { .type = I915_WA_PLATFORM, \
+ .flags = I915_WA_SUBPLATFORM | I915_WA_REVID, \
+ .subplatform = (sp), \
+ .platform = (p), \
+ .start = (s), \
+ .end = (e) \
+ }
+
+#define wa_rule_subplatform_gtrevid(p, sp, s, e) \
+ { .type = I915_WA_PLATFORM, \
+ .flags = I915_WA_SUBPLATFORM | I915_WA_GTREVID, \
+ .subplatform = (sp), \
+ .platform = (p), \
+ .start = (s), \
+ .end = (e) \
+ }
+
+#include "intel_workarounds_table.h"
+
+static __always_inline bool
+__is_platform(const struct drm_i915_private *i915, enum intel_platform p)
+{
+ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+ const unsigned int pi = __platform_mask_index(info, p);
+ const unsigned int pb = __platform_mask_bit(info, p);
+
+ return info->platform_mask[pi] & BIT(pb);
+}
+
+static __always_inline bool
+__is_subplatform(const struct drm_i915_private *i915,
+ enum intel_platform p, unsigned int s)
+{
+ const struct intel_runtime_info *info = RUNTIME_INFO(i915);
+ const unsigned int pi = __platform_mask_index(info, p);
+ const unsigned int pb = __platform_mask_bit(info, p);
+ const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
+ const u32 mask = info->platform_mask[pi];
+
+ /* Shift and test on the MSB position so sign flag can be used. */
+ return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
+}
+
+static bool
+__match_platform(struct drm_i915_private *i915, const struct i915_wa_rule *rule)
+{
+ if (!__is_platform(i915, rule->platform))
+ return false;
+
+ if (rule->flags & I915_WA_SUBPLATFORM) {
+ unsigned int s, s__;
+ bool is = false;
+
+ for (s = 0, s__ = rule->subplatform;
+ s__ && s < BIT(INTEL_SUBPLATFORM_BITS);
+ s++, s__ >>= 1) {
+ if ((s__ & 1) &&
+ __is_subplatform(i915, rule->platform, s)) {
+ is = true;
+ break;
+ }
+ }
+
+ if (!is)
+ return false;
+ }
+
+ if (rule->flags & I915_WA_REVID) {
+ if (!IS_REVID(i915, rule->start, rule->end))
+ return false;
+ }
+
+ if (rule->flags & I915_WA_GTREVID) {
+ switch (rule->platform) {
+ case INTEL_KABYLAKE:
+ if (!IS_KBL_GT_REVID(i915, rule->start, rule->end))
+ return false;
+ break;
+ case INTEL_TIGERLAKE:
+ if (!IS_TGL_GT_REVID(i915, rule->start, rule->end))
+ return false;
+ break;
+ default:
+ MISSING_CASE(rule->platform);
+ };
+ }
+
+ return true;
+}
+
+struct wa_context {
+ struct drm_i915_private *i915;
+ union {
+ struct {
+ struct intel_engine_cs *engine;
+ };
+ };
+};
+
+static void
+__process_was(const struct i915_wa_ng *list,
+ unsigned int type,
+ void (*process)(const struct i915_wa_ng *,
+ const struct wa_context *wac),
+ const struct wa_context *wac)
+{
+ const struct i915_wa_ng *wa;
+
+ for (wa = list; wa->type; wa++) {
+ bool platform_matched = false;
+ bool engine_matched = false;
+ bool gen_matched = false;
+ const struct i915_wa_rule *rule;
+
+ if (wa->type != type)
+ continue;
+// printk("considering %s\n", wa->name);
+ for (rule = wa->rules; rule->type; rule++) {
+ switch (rule->type) {
+ case I915_WA_ENGINE_CLASS:
+ GEM_BUG_ON(wa->type != I915_WA_ENGINE);
+ GEM_WARN_ON(engine_matched);
+
+ engine_matched = BIT(wac->engine->class) &
+ rule->class_mask;
+ break;
+ case I915_WA_PLATFORM:
+ platform_matched |= __match_platform(wac->i915,
+ rule);
+ break;
+ case I915_WA_GENMASK:
+ GEM_WARN_ON(gen_matched);
+
+ gen_matched = INTEL_INFO(wac->i915)->gen_mask &
+ rule->genmask;
+ break;
+ default:
+ MISSING_CASE(rule->type);
+ }
+ }
+
+// printk(" g%u p%u e%u\n", gen_matched, platform_matched, engine_matched);
+ if ((type != I915_WA_ENGINE || engine_matched) &&
+ (platform_matched || gen_matched)) {
+ process(wa, wac);
+#if !IS_ENABLED(CONFIG_DRM_I915_DEBUG)
+ break;
+#endif
+ }
+ }
+}
+
static void
rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
@@ -2048,9 +2291,16 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
xcs_engine_wa_init(engine, wal);
}
+static void
+__print_engine_wa(const struct i915_wa_ng *wa, const struct wa_context *wac)
+{
+ printk("INIT-ENGINE-WA: %s: %s\n", wac->engine->name, wa->name);
+}
+
void intel_engine_init_workarounds(struct intel_engine_cs *engine)
{
struct i915_wa_list *wal = &engine->wa_list;
+ struct wa_context wac = { .i915 = engine->i915, .engine = engine };
if (INTEL_GEN(engine->i915) < 4)
return;
@@ -2058,11 +2308,41 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
wa_init_start(wal, "engine", engine->name);
engine_init_workarounds(engine, wal);
wa_init_finish(wal);
+
+ __process_was(__wa_list, I915_WA_ENGINE, __print_engine_wa, &wac);
+}
+
+static void
+__apply_engine_wa(const struct i915_wa_ng *wa_, const struct wa_context *wac)
+{
+ struct intel_uncore *uncore = wac->engine->uncore;
+ const struct i915_wa *wa = &wa_->wa;
+ i915_reg_t reg = wa->reg;
+
+ if (wa_->flags & I915_WA_MMIO_BASE)
+ reg.reg += wac->engine->mmio_base;
+
+ if (wa->clr)
+ intel_uncore_rmw(uncore, reg, wa->clr, wa->set);
+ else
+ intel_uncore_write(uncore, reg, wa->set);
+
+ printk("APPLIED-ENGINE-WA: %s: %s\n", wac->engine->name, wa_->name);
+
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) &&
+ !(wa_->flags & I915_WA_SKIP_VERIFY))
+ wa_verify(wa,
+ intel_uncore_read(uncore, reg),
+ wac->engine->name,
+ "application");
}
void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
{
- wa_list_apply(engine->uncore, &engine->wa_list);
+ struct wa_context wac = { .i915 = engine->i915, .engine = engine };
+
+// wa_list_apply(engine->uncore, &engine->wa_list);
+ __process_was(__wa_list, I915_WA_ENGINE, __apply_engine_wa, &wac);
}
static struct i915_vma *
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_table.h b/drivers/gpu/drm/i915/gt/intel_workarounds_table.h
new file mode 100644
index 000000000000..90bba1fbdb87
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_table.h
@@ -0,0 +1,471 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2020 Intel Corporation
+ */
+
+/*
+ * TODO Consolidated list of gt/engine/ctx wa - single list for application
+ * and verification - no runtime copies is the end game.
+ */
+static const struct i915_wa_ng __wa_list[] = {
+ {
+ "Wa_1607138336:tgl[a0],dg1[a0];"
+ "Wa_1607063988:tgl[a0],dg1[a0]",
+ wa_engine,
+ wa_or(GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_DG1,
+ DG1_REVID_A0, DG1_REVID_A0),
+ wa_rule_subplatform_gtrevid(INTEL_TIGERLAKE,
+ BIT(INTEL_SUBPLATFORM_ULT) |
+ BIT(INTEL_SUBPLATFORM_ULX),
+ TGL_REVID_A0, TGL_REVID_A0),
+ wa_rules_end
+ },
+ {
+ /* (see also Wa_1606682166:icl) */
+ "Wa_1606679103:tgl",
+ wa_engine,
+ wa_or(GEN7_SARCHKMD, GEN7_DISABLE_SAMPLER_PREFETCH),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_subplatform_gtrevid(INTEL_TIGERLAKE,
+ BIT(INTEL_SUBPLATFORM_ULT) |
+ BIT(INTEL_SUBPLATFORM_ULX),
+ TGL_REVID_A0, TGL_REVID_A0),
+ wa_rules_end
+ },
+ {
+ "Wa_1606931601:tgl,rkl,dg1",
+ wa_engine,
+ wa_en(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_DG1), /* TODO platform mask? */
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ "Wa_1407928979:tgl A*;"
+ "Wa_18011464164:tgl[B0+],dg1[B0+];"
+ "Wa_22010931296:tgl[B0+],dg1[B0+];"
+ "Wa_14010919138:rkl,dg1",
+ wa_engine,
+ wa_or(GEN7_FF_THREAD_MODE,
+ GEN12_FF_TESSELATION_DOP_GATE_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_DG1),
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ "Wa_1409804808:tgl,rkl,dg1[a0]",
+ wa_engine,
+ wa_en(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_DG1,
+ DG1_REVID_A0, DG1_REVID_A0),
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ "Wa_1409085225:tgl;"
+ "Wa_14010229206:tgl,rkl,dg1[a0]",
+ wa_engine,
+ wa_en(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_DG1,
+ DG1_REVID_A0, DG1_REVID_A0),
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ /*
+ * On TGL and RKL there are multiple entries for this WA in the
+ * BSpec; some indicate this is an A0-only WA, others indicate
+ * it applies to all steppings so we trust the "all steppings."
+ * For DG1 this only applies to A0.
+ */
+ "Wa_1607030317:tgl;"
+ "Wa_1607186500:tgl;"
+ "Wa_1607297627:tgl,rkl,dg1[a0]",
+ wa_engine,
+ wa_en(GEN6_RC_SLEEP_PSMI_CONTROL,
+ GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
+ GEN8_RC_SEMA_IDLE_MSG_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_DG1,
+ DG1_REVID_A0, DG1_REVID_A0),
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ "Wa_1606700617:tgl;"
+ "Wa_22010271021:tgl,rkl",
+ wa_engine,
+ wa_en(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_DG1,
+ DG1_REVID_A0, DG1_REVID_A0),
+ wa_rule_platform(INTEL_ROCKETLAKE),
+ wa_rule_platform(INTEL_TIGERLAKE),
+ wa_rules_end
+ },
+ {
+ "Wa_1406941453:gen12",
+ wa_engine,
+ wa_en(GEN10_SAMPLER_MODE, ENABLE_SMALLPL),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(12),
+ wa_rules_end
+ },
+ {
+ /* This is not an Wa. Enable for better image quality */
+ "_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE",
+ wa_engine,
+ wa_en(_3D_CHICKEN3, _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "WaPipelineFlushCoherentLines:icl",
+ wa_engine,
+ wa_or(GEN8_L3SQCREG4, GEN8_LQSC_FLUSH_COHERENT_LINES),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ /* Formerly known as WaGAPZPriorityScheme */
+ "Wa_1405543622:icl",
+ wa_engine,
+ wa_or(GEN8_GARBCNTL, GEN11_ARBITRATION_PRIO_ORDER_MASK),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ /* Formerly known as WaL3BankAddressHashing */
+ "Wa_1604223664:icl",
+ wa_engine,
+ wa_masked_or(GEN8_GARBCNTL,
+ GEN11_HASH_CTRL_EXCL_MASK,
+ GEN11_HASH_CTRL_EXCL_BIT0),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ /* Formerly known as WaL3BankAddressHashing */
+ "Wa_1604223664:icl",
+ wa_engine,
+ wa_masked_or(GEN11_GLBLINVL,
+ GEN11_BANK_HASH_ADDR_EXCL_MASK,
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ /* Formerly known as WaDisableCleanEvicts */
+ "Wa_1405733216:icl",
+ wa_engine,
+ wa_or(GEN8_L3SQCREG4, GEN11_LQSC_CLEAN_EVICT_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "WaForwardProgressSoftReset:icl",
+ wa_engine,
+ wa_or(GEN10_SCRATCH_LNCF2,
+ PMFLUSHDONE_LNICRSDROP |
+ PMFLUSH_GAPL3UNBLOCK |
+ PMFLUSHDONE_LNEBLK),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1606682166:icl",
+ wa_engine,
+ wa_or(GEN7_SARCHKMD, GEN7_DISABLE_SAMPLER_PREFETCH),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1409178092:icl",
+ wa_engine,
+ wa_masked_or(GEN11_SCRATCH2,
+ GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
+ 0),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "WaEnable32PlaneMode:icl",
+ wa_engine,
+ wa_en(GEN9_CSFE_CHICKEN1_RCS, GEN11_ENABLE_32_PLANE_MODE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1408615072:icl,ehl (vsunit);"
+ "Wa_1407596294:icl,ehl (hsunit)",
+ wa_engine,
+ wa_or(UNSLICE_UNIT_LEVEL_CLKGATE,
+ VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1407352427:icl,ehl",
+ wa_engine,
+ wa_or(UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1406680159:icl,ehl",
+ wa_engine,
+ wa_or(SUBSLICE_UNIT_LEVEL_CLKGATE, GWUNIT_CLKGATE_DIS),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1408767742:icl[a2..forever],ehl[all];"
+ "Wa_1605460711:icl[a0..c0]",
+ wa_engine,
+ wa_or(GEN7_FF_THREAD_MODE,
+ GEN12_FF_TESSELATION_DOP_GATE_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(11),
+ wa_rules_end
+ },
+ {
+ "Wa_1406609255:icl (pre-prod)",
+ wa_engine,
+ wa_or(GEN7_SARCHKMD, GEN7_DISABLE_DEMAND_PREFETCH),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform_revid(INTEL_ICELAKE,
+ ICL_REVID_A0, ICL_REVID_B0),
+ wa_rules_end
+ },
+ {
+ "Wa_22010271021:ehl",
+ wa_engine,
+ wa_en(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_JASPERLAKE),
+ wa_rule_platform(INTEL_ELKHARTLAKE),
+ wa_rules_end
+ },
+ {
+ "FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl",
+ wa_engine,
+ wa_en(GEN7_FF_SLICE_CS_CHICKEN1, GEN9_FFSC_PERCTX_PREEMPT_CTRL),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen_range(9, 12),
+ wa_rules_end
+ },
+ {
+ "WaEnableGapsTsvCreditFix:skl,kbl,cfl",
+ wa_engine,
+ wa_or(GEN8_GARBCNTL, GEN9_GAPS_TSV_CREDIT_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_SKYLAKE),
+ wa_rule_platform(INTEL_KABYLAKE),
+ wa_rule_platform(INTEL_COFFEELAKE),
+ wa_rule_platform(INTEL_COMETLAKE),
+ wa_rules_end
+ },
+ {
+ "WaDisablePooledEuLoadBalancingFix:bxt",
+ wa_engine,
+ wa_en(FF_SLICE_CS_CHICKEN2,
+ GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_BROXTON),
+ wa_rules_end
+ },
+ {
+ "WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl",
+ wa_engine,
+ wa_en(GEN9_CSFE_CHICKEN1_RCS,
+ GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(9),
+ wa_rules_end
+ },
+ {
+ "WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl",
+ wa_engine,
+ wa_or(BDW_SCRATCH1, GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(9),
+ wa_rules_end
+ },
+ {
+ "WaOCLCoherentLineFlush:skl,bxt,kbl,cfl",
+ wa_engine,
+ wa_or(GEN8_L3SQCREG4, GEN8_LQSC_FLUSH_COHERENT_LINES),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(9),
+ wa_rules_end
+ },
+ {
+ "WaProgramL3SqcReg1DefaultForPerf:bxt,glk",
+ wa_engine,
+ wa_masked_or(GEN8_L3SQCREG1,
+ L3_PRIO_CREDITS_MASK,
+ L3_GENERAL_PRIO_CREDITS(62) |
+ L3_HIGH_PRIO_CREDITS(2)),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_platform(INTEL_BROXTON),
+ wa_rule_platform(INTEL_GEMINILAKE),
+ wa_rules_end
+ },
+ {
+ "WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw",
+ wa_engine,
+ wa_en(GFX_MODE_GEN7,
+ GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(7),
+ wa_rules_end
+ },
+ {
+ /*
+ * We need to disable the AsyncFlip performance optimisations in
+ * order to use MI_WAIT_FOR_EVENT within the CS. It should
+ * already be programmed to '1' on all products.
+ */
+ "WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv",
+ wa_engine,
+ wa_en(MI_MODE, ASYNC_FLIP_PERF_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen_range(6, 7),
+ wa_rules_end
+ },
+ {
+ /*
+ * Required for the hardware to program scanline values for
+ * waiting
+ */
+ "WaEnableFlushTlbInvalidationMode:snb",
+ wa_engine,
+ wa_en(GFX_MODE, GFX_TLB_INVALIDATE_EXPLICIT),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(6),
+ wa_rules_end
+ },
+ {
+ /*
+ * From the Sandybridge PRM, volume 1 part 3, page 24:
+ * "If this bit is set, STCunit will have LRA as replacement
+ * policy. [...] This bit must be reset. LRA replacement
+ * policy is not supported."
+ */
+ "LRANotSupported",
+ wa_engine,
+ wa_dis(CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(6),
+ wa_rules_end
+ },
+ {
+ "WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb",
+ wa_engine,
+ /* XXX bit doesn't stick on Broadwater */
+ .flags = I915_WA_SKIP_VERIFY,
+ wa_en(MI_MODE, VS_TIMER_DISPATCH),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen_range(4, 6),
+ wa_rules_end
+ },
+ {
+ /*
+ * Disable CONSTANT_BUFFER before it is loaded from the context
+ * image. For as it is loaded, it is executed and the stored
+ * address may no longer be valid, leading to a GPU hang.
+ *
+ * This imposes the requirement that userspace reload their
+ * CONSTANT_BUFFER on every batch, fortunately a requirement
+ * they are already accustomed to from before contexts were
+ * enabled.
+ */
+ "DisableConstantBuffer",
+ wa_engine,
+ /* XXX bit doesn't stick on Broadwater */
+ .flags = I915_WA_SKIP_VERIFY,
+ wa_en(ECOSKPD, ECO_CONSTANT_BUFFER_SR_DISABLE),
+ wa_rules_start
+ wa_rule_engine_class(RENDER_CLASS),
+ wa_rule_gen(4),
+ wa_rules_end
+ },
+
+ /* xcs */
+ {
+ "WaKBLVECSSemaphoreWaitPoll:kbl",
+ wa_engine,
+ .flags = I915_WA_MMIO_BASE,
+ wa_set(_MMIO(RING_SEMA_WAIT_POLL_OFFSET), 1),
+ wa_rules_start
+ wa_rule_not_engine_class(RENDER_CLASS),
+ wa_rule_platform_gtrevid(INTEL_KABYLAKE,
+ KBL_REVID_A0, KBL_REVID_E0),
+ wa_rules_end
+ },
+
+ /* mark end */
+ { }
+};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..f974342cd96b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2535,7 +2535,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define RESET_CTL_READY_TO_RESET REG_BIT(1)
#define RESET_CTL_REQUEST_RESET REG_BIT(0)
-#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
+#define RING_SEMA_WAIT_POLL_OFFSET (0x24c)
+#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + RING_SEMA_WAIT_POLL_OFFSET)
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
--
2.25.1
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