[PATCH] Yet again check uncore spin lock and mmio write times

Stanislav Lisovskiy stanislav.lisovskiy at intel.com
Thu Oct 1 15:32:12 UTC 2020


---
 drivers/gpu/drm/i915/display/intel_display.c | 49 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_sprite.c  | 17 +++++++
 2 files changed, 66 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 753f202ef6a0..70adb83d5138 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15381,6 +15381,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	bool modeset = needs_modeset(new_crtc_state);
+	ktime_t t = ktime_get(), t2;
 
 	/*
 	 * During modesets pipe configuration was programmed as the
@@ -15391,20 +15392,56 @@ static void commit_pipe_config(struct intel_atomic_state *state,
 		    new_crtc_state->update_pipe)
 			intel_color_commit(new_crtc_state);
 
+		t2 = ktime_get();
+		if (ktime_us_delta(t2, t) >= 50)
+		    drm_warn(&dev_priv->drm,
+				 "intel_color_commit took %llu us!\n", ktime_us_delta(t2, t));
+
+		t = ktime_get();
 		if (INTEL_GEN(dev_priv) >= 9)
 			skl_detach_scalers(new_crtc_state);
 
+		t2 = ktime_get();
+                if (ktime_us_delta(t2, t) >= 50)
+                    drm_warn(&dev_priv->drm,
+                                 "skl_detach_scalers took %llu us!\n", ktime_us_delta(t2, t));
+
+		t = ktime_get();
 		if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 			bdw_set_pipemisc(new_crtc_state);
 
+		t2 = ktime_get();
+                if (ktime_us_delta(t2, t) >= 50)
+                    drm_warn(&dev_priv->drm,
+                                 "bdw_set_pipemisc took %llu us!\n", ktime_us_delta(t2, t));
+
+		t = ktime_get();
 		if (new_crtc_state->update_pipe)
 			intel_pipe_fastset(old_crtc_state, new_crtc_state);
 
+		t2 = ktime_get();
+                if (ktime_us_delta(t2, t) >= 50)
+                    drm_warn(&dev_priv->drm,
+                                 "intel_pipe_fastset took %llu us!\n", ktime_us_delta(t2, t));
+
+		t = ktime_get();
 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
+
+		t2 = ktime_get();
+                if (ktime_us_delta(t2, t) >= 50)
+                    drm_warn(&dev_priv->drm,
+                                 "intel_psr2_program_trans_man_trk_ctl took %llu us!\n", ktime_us_delta(t2, t));
+
 	}
 
+	t = ktime_get();
 	if (dev_priv->display.atomic_update_watermarks)
 		dev_priv->display.atomic_update_watermarks(state, crtc);
+
+	t2 = ktime_get();
+	if (ktime_us_delta(t2, t) >= 50)
+            drm_warn(&dev_priv->drm,
+                     "atomic_update_watermarks took %llu us!\n", ktime_us_delta(t2, t));
 }
 
 static void intel_enable_crtc(struct intel_atomic_state *state,
@@ -15434,6 +15471,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	bool modeset = needs_modeset(new_crtc_state);
+	ktime_t t, t2;
 
 	if (!modeset) {
 		if (new_crtc_state->preload_luts &&
@@ -15455,13 +15493,24 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(new_crtc_state);
 
+	t = ktime_get();
 	commit_pipe_config(state, crtc);
+        t2 = ktime_get();
+        if (ktime_us_delta(t2, t) >= 50)
+            drm_warn(&dev_priv->drm,
+                     "commit_pipe_config took %llu us!\n", ktime_us_delta(t2, t));
 
+	t = ktime_get();
 	if (INTEL_GEN(dev_priv) >= 9)
 		skl_update_planes_on_crtc(state, crtc);
 	else
 		i9xx_update_planes_on_crtc(state, crtc);
 
+        t2 = ktime_get();
+        if (ktime_us_delta(t2, t) >= 50)
+            drm_warn(&dev_priv->drm,
+                     "updating planes took %llu us!\n", ktime_us_delta(t2, t));
+
 	intel_pipe_update_end(new_crtc_state);
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2da11ab6343c..45cedfdc632c 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -199,11 +199,16 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
+	ktime_t t = ktime_get();
 	int scanline_end = intel_get_crtc_scanline(crtc);
 	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 	ktime_t end_vbl_time = ktime_get();
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
+        if (ktime_us_delta(end_vbl_time, t) >= 50)
+                    drm_warn(&dev_priv->drm,
+                                 "get crtc scanline and get vblank took %llu us!\n", ktime_us_delta(end_vbl_time, t));
+
 	if (new_crtc_state->uapi.async_flip)
 		return;
 
@@ -668,6 +673,7 @@ skl_program_plane(struct intel_plane *plane,
 	unsigned long irqflags;
 	u32 keymsk, keymax;
 	u32 plane_ctl = plane_state->ctl;
+	ktime_t t, t2;
 
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
@@ -691,8 +697,14 @@ skl_program_plane(struct intel_plane *plane,
 		crtc_y = 0;
 	}
 
+	t = ktime_get();
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+	t2 = ktime_get();
+        if (ktime_us_delta(t2, t) >= 50)
+            drm_warn(&dev_priv->drm,
+                     "spinlock in skl_program_plane took %llu us!\n", ktime_us_delta(t2, t));
 
+	t = ktime_get();
 	intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
 	intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
 			  (crtc_y << 16) | crtc_x);
@@ -740,6 +752,11 @@ skl_program_plane(struct intel_plane *plane,
 	if (plane_state->scaler_id >= 0)
 		skl_program_scaler(plane, crtc_state, plane_state);
 
+	t2 = ktime_get();
+        if (ktime_us_delta(t2, t) >= 50)
+            drm_warn(&dev_priv->drm,
+                     "program plane took %llu us!\n", ktime_us_delta(t2, t));
+
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-- 
2.24.1.485.gad05a3d8e5



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