[PATCH] drm/i915/pll: Centralize PLL_ENABLE register lookup

[Ville Syrjälä]

On Wed, Sep 09, 2020 at 12:22:59PM -0700, Anusha Srivatsa wrote:
> We currenty check for platform at multiple parts in the driver
> to grab the correct PLL. Let us begin to centralize it through a
> helper function.
> 
> v2: s/intel_get_pll_enable_reg()/intel_combo_pll_enable_reg() (Ville)
> 
> v3: Clean up combo_pll_disable() (Rodrigo)
> 
> Suggested-by: Matt Roper <matthew.d.roper at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++++--------
>  1 file changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c9013f8f766f..2ab0ed1f4417 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -147,6 +147,18 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			pll->info->name, onoff(state), onoff(cur_state));
>  }
>  
> +static

Somewhat weird place to wrap the line here.

> +i915_reg_t intel_combo_pll_enable_reg(struct drm_i915_private *dev_priv,
> +				    struct intel_shared_dpll *pll)

-- 
Ville Syrjälä
Intel