[PATCH i-g-t 3/6] MMAP_FIXED_SQUASH
Thomas Hellström
thomas.hellstrom at linux.intel.com
Fri Aug 6 09:42:06 UTC 2021
From: Matthew Auld <matthew.auld at intel.com>
Squashed commit of the following:
commit 10fb85ff35c7cc893b5f16e5392cbbedc376e4de
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:48 2021 +0100
tests/i915/gem_exec_fence: use device_coherent mmap
We lost explicit WC mmaps on discrete, where we now only support FIXED,
however such mappings should be device coherent. In gem_exec_fence it
looks like we can just use mmap__device_coherent, which should also work
on discrete platforms, while still using an explicit WC mmap on
integrated platforms.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit 6d80341f65d0d2711c4dad4e4aa38cdaf5753247
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:47 2021 +0100
lib/i915/gem_mman: add helper query for has_device_coherent
Might be useful in some tests, where we are not explicitly testing WC
maps, but rather just require something that is "device coherent", which
should also play nice on discrete platforms.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit c8e7d93868655a531ada8ed992eb227eba9a7707
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:46 2021 +0100
tests/i915/module_load: update for discrete
The set_caching ioctl is gone for discrete, and now just returns
-ENODEV. Update the gem_sanitycheck to account for that. After this we
should be back to just having the breakage caused by missing reloc
support for the reload testcase.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
commit 6554046446c910d0b6da14dd88f0b9a0d05235d7
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:45 2021 +0100
lib/ioctl_wrappers: update set_domain for discrete
On discrete set_domain is now gone, instead we just need to add the
wait.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
commit cfc5faae2e1896a9720240c4123dc1291718d049
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:44 2021 +0100
lib/intel_bufops: update mmap_{read, write} for discrete
On discrete we can no longer call get_caching or set_domain, and the
mmap mode must be FIXED.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit bc5cb44986193087f9023910a4c8668d83330f37
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:43 2021 +0100
lib/ioctl_wrappers: update mmap_{read, write} for discrete
We can no longer just call get_caching or set_domain, and the mmap mode
must be FIXED. This should bring back gem_exec_basic and a few others in
CI on DG1.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit f84d97911fdd5bebbbbd0a1bb2cce109ad3202eb
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:42 2021 +0100
lib/i915/gem_mman: update mmap_offset_types with FIXED
We need to also iterate the fixed mode in the tests which rely on this.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit 4d5804bef71dcab4d5c7014cce01e13c4adb78ae
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:41 2021 +0100
lib/i915/gem_mman: add fixed mode to gem_mmap__cpu
On discrete we only support the new fixed mode.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit 87d57439921a0e3ad58241ae816a6b82e0c87836
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:40 2021 +0100
lib/i915/gem_mman: add fixed mode to gem_mmap_offset__cpu
On discrete we only support the new fixed mode.
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit 5391c4a4d5dec4cd21699a753eb32674f570b78b
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:39 2021 +0100
lib/i915/gem_mman: add fixed mode to mmap__device_coherent
On discrete we need to fallback to this mode.
v2(Ashutosh):
- Move it up the pecking order
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
commit 61af32f1b87ee9b8e23d4c85617b486965b063dd
Author: Matthew Auld <matthew.auld at intel.com>
Date: Fri Jul 30 09:53:38 2021 +0100
lib/i915/gem_mman: add FIXED mmap mode
We need this for discrete.
v2(Ashutosh):
- use the new i915_drm_local.h infrastructure, and drop the LOCAL prefix
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Ramalingam C <ramalingam.c at intel.com>
---
lib/i915/gem_mman.c | 96 +++++++++++++++++++++++++++++++++--
lib/i915/gem_mman.h | 15 ++++++
lib/i915/i915_drm_local.h | 2 +
lib/intel_bufops.c | 25 ++++++++-
lib/ioctl_wrappers.c | 32 ++++++++++--
tests/i915/gem_exec_fence.c | 16 +++---
tests/i915/i915_module_load.c | 9 +++-
7 files changed, 177 insertions(+), 18 deletions(-)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 4b4f2114..0406a0b9 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -27,6 +27,7 @@
#include <errno.h>
#include "igt_core.h"
+#include "igt_gt.h"
#include "igt_device.h"
#include "ioctl_wrappers.h"
#include "intel_chipset.h"
@@ -196,6 +197,45 @@ bool gem_mmap_offset__has_wc(int fd)
return has_wc > 0;
}
+bool gem_mmap__has_device_coherent(int fd)
+{
+ struct drm_i915_gem_mmap_offset arg;
+ bool supported;
+
+ if (gem_mmap__has_wc(fd))
+ return true;
+
+ /* Maybe we still have GTT mmaps? */
+ memset(&arg, 0, sizeof(arg));
+ arg.handle = gem_create(fd, 4096);
+ arg.offset = 0;
+ arg.flags = I915_MMAP_OFFSET_GTT;
+ supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+ &arg) == 0;
+ gem_close(fd, arg.handle);
+
+ errno = 0;
+
+ if (supported)
+ return true;
+
+ /*
+ * Maybe this is a discrete device, which only supports fixed mmaps?
+ * Such mappings should also be considered device coherent.
+ */
+ memset(&arg, 0, sizeof(arg));
+ arg.handle = gem_create(fd, 4096);
+ arg.offset = 0;
+ arg.flags = I915_MMAP_OFFSET_FIXED;
+ supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+ &arg) == 0;
+ gem_close(fd, arg.handle);
+
+ errno = 0;
+
+ return supported;
+}
+
/**
* __gem_mmap:
* @fd: open i915 drm file descriptor
@@ -381,9 +421,11 @@ void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
{
void *ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
I915_MMAP_OFFSET_WC);
+
+ if (!ptr)
+ ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
if (!ptr)
ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
-
if (!ptr)
ptr = __gem_mmap__gtt(fd, handle, size, prot);
@@ -433,7 +475,13 @@ void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
*/
void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
{
- return __gem_mmap(fd, handle, offset, size, prot, 0);
+ void *ptr;
+
+ ptr = __gem_mmap(fd, handle, offset, size, prot, 0);
+ if (!ptr)
+ ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+ return ptr;
}
/**
@@ -471,8 +519,14 @@ void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, uns
void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot)
{
- return __gem_mmap_offset(fd, handle, offset, size, prot,
+ void *ptr;
+
+ ptr = __gem_mmap_offset(fd, handle, offset, size, prot,
I915_MMAP_OFFSET_WB);
+ if (!ptr)
+ ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+ return ptr;
}
/**
@@ -497,6 +551,41 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
return ptr;
}
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot)
+{
+ return __gem_mmap_offset(fd, handle, offset, size, prot,
+ I915_MMAP_OFFSET_FIXED);
+}
+
+/**
+ * gem_mmap_offset__fixed: Used to mmap objects on discrete platforms
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Like __gem_mmap_offset__fixed() except we assert on failure.
+ *
+ * For discrete the caching attributes for the pages are fixed at allocation
+ * time, and can't be changed. The FIXED mode will simply use the same caching *
+ * mode of the allocated pages. This mode will always be coherent with GPU
+ * access.
+ *
+ * On non-discrete platforms this mode is not supported.
+ *
+ * Returns: A pointer to the created memory mapping
+ */
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot)
+{
+ void *ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+ igt_assert(ptr);
+ return ptr;
+}
+
/**
* __gem_mmap__cpu_coherent:
* @fd: open i915 drm file descriptor
@@ -571,6 +660,7 @@ const struct mmap_offset mmap_offset_types[] = {
{ "wb", I915_MMAP_OFFSET_WB, I915_GEM_DOMAIN_CPU },
{ "wc", I915_MMAP_OFFSET_WC, I915_GEM_DOMAIN_WC },
{ "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC },
+ { "fixed", I915_MMAP_OFFSET_FIXED, 0},
{},
};
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 5695d2ad..5966ddb5 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -37,8 +37,11 @@ bool gem_mmap_offset__has_wc(int fd);
void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot);
void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+bool gem_mmap__has_device_coherent(int fd);
void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
@@ -54,6 +57,8 @@ void *__gem_mmap_offset__cpu(int fd, uint32_t handle, uint64_t offset,
void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot);
void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
@@ -92,6 +97,16 @@ int gem_munmap(void *ptr, uint64_t size);
*/
#define gem_require_mmap_offset_wc(fd) igt_require(gem_mmap_offset__has_wc(fd))
+/**
+ * gem_require_mmap_offset_device_coherent:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether direct (i.e. cpu access path, bypassing
+ * the gtt) write-combine memory mappings are available, or fixed mapping for
+ * discrete. Automatically skips through igt_require() if not.
+ */
+#define gem_require_mmap_device_coherent(fd) igt_require(gem_mmap__has_device_coherent(fd))
+
extern const struct mmap_offset {
const char *name;
unsigned int type;
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index dd646aed..0e3cef81 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -20,6 +20,8 @@ extern "C" {
* clean these up when kernel uapi headers are sync'd.
*/
+#define I915_MMAP_OFFSET_FIXED 4
+
#if defined(__cplusplus)
}
#endif
diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 3ce68663..faca4406 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -424,7 +424,18 @@ static void *mmap_write(int fd, struct intel_buf *buf)
{
void *map = NULL;
- if (is_cache_coherent(fd, buf->handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+ * set/get_caching and set_domain are no longer supported on
+ * discrete, also the only mmap mode supportd is FIXED.
+ */
+ map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+ buf->surface[0].size,
+ PROT_READ | PROT_WRITE);
+ igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+ }
+
+ if (!map && is_cache_coherent(fd, buf->handle)) {
map = __gem_mmap_offset__cpu(fd, buf->handle, 0, buf->surface[0].size,
PROT_READ | PROT_WRITE);
if (!map)
@@ -455,7 +466,17 @@ static void *mmap_read(int fd, struct intel_buf *buf)
{
void *map = NULL;
- if (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+ * set/get_caching and set_domain are no longer supported on
+ * discrete, also the only supported mmap mode is FIXED.
+ */
+ map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+ buf->surface[0].size, PROT_READ);
+ igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+ }
+
+ if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle))) {
map = __gem_mmap_offset__cpu(fd, buf->handle, 0,
buf->surface[0].size, PROT_READ);
if (!map)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 25c5e495..09eb3ce7 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -339,7 +339,18 @@ static void mmap_write(int fd, uint32_t handle, uint64_t offset,
if (!length)
return;
- if (is_cache_coherent(fd, handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+ * set/get_caching and set_domain are no longer supported on
+ * discrete, also the only mmap mode supportd is FIXED.
+ */
+ map = gem_mmap_offset__fixed(fd, handle, 0,
+ offset + length,
+ PROT_READ | PROT_WRITE);
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ }
+
+ if (!map && is_cache_coherent(fd, handle)) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0, offset + length,
PROT_READ | PROT_WRITE);
@@ -369,7 +380,17 @@ static void mmap_read(int fd, uint32_t handle, uint64_t offset, void *buf, uint6
if (!length)
return;
- if (gem_has_llc(fd) || is_cache_coherent(fd, handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+ * set/get_caching and set_domain are no longer supported on
+ * discrete, also the only supported mmap mode is FIXED.
+ */
+ map = gem_mmap_offset__fixed(fd, handle, 0,
+ offset + length, PROT_READ);
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ }
+
+ if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, handle))) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0,
offset + length, PROT_READ);
@@ -544,7 +565,12 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
*/
void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
{
- igt_assert_eq(__gem_set_domain(fd, handle, read, write), 0);
+ int ret = __gem_set_domain(fd, handle, read, write);
+
+ if (ret == -ENODEV && gem_has_lmem(fd))
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ else
+ igt_assert_eq(ret, 0);
}
/**
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 52335c91..c558f4df 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -162,7 +162,7 @@ static void test_fence_busy(int fd, const intel_ctx_t *ctx,
obj.handle = gem_create(fd, 4096);
obj.offset = get_offset(ahnd, obj.handle, 4096, 0);
- batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+ batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
gem_set_domain(fd, obj.handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
@@ -262,7 +262,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t *ctx, unsigned flags)
obj.offset = get_offset(ahnd, obj.handle, 4096, 0);
igt_assert(obj.offset != -1);
- batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+ batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
gem_set_domain(fd, obj.handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
@@ -383,7 +383,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
scratch_offset = get_offset(ahnd, scratch, 4096, 0);
- out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
+ out = gem_mmap__device_coherent(fd, scratch, 0, 4096, PROT_WRITE);
gem_set_domain(fd, scratch,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
@@ -655,7 +655,7 @@ static void test_parallel(int i915, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e2;
const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
uint32_t scratch = gem_create(i915, 4096);
- uint32_t *out = gem_mmap__wc(i915, scratch, 0, 4096, PROT_READ);
+ uint32_t *out = gem_mmap__device_coherent(i915, scratch, 0, 4096, PROT_READ);
uint32_t handle[I915_EXEC_RING_MASK];
IGT_CORK_FENCE(cork);
igt_spin_t *spin;
@@ -2909,7 +2909,7 @@ static void test_syncobj_timeline_chain_engines(int fd, const intel_ctx_cfg_t *c
gem_sync(fd, ctx.engine_counter_object.handle);
- counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+ counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2975,7 +2975,7 @@ static void test_syncobj_stationary_timeline_chain_engines(int fd, const intel_c
gem_sync(fd, ctx.engine_counter_object.handle);
- counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+ counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -3036,7 +3036,7 @@ static void test_syncobj_backward_timeline_chain_engines(int fd, const intel_ctx
gem_sync(fd, ctx.engine_counter_object.handle);
- counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
+ counter_output = gem_mmap__device_coherent(fd, ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -3059,7 +3059,7 @@ igt_main
i915 = drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
igt_require(gem_has_exec_fence(i915));
- gem_require_mmap_wc(i915);
+ gem_require_mmap_device_coherent(i915);
ctx = intel_ctx_create_all_physical(i915);
gem_submission_print_method(i915);
diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 993c7832..168b8ca2 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -193,17 +193,22 @@ static void gem_sanitycheck(void)
{
struct drm_i915_gem_caching args = {};
int i915 = __drm_open_driver(DRIVER_INTEL);
+ int expected;
int err;
+ expected = -ENOENT;
+ if (gem_has_lmem(i915))
+ expected = -ENODEV;
+
err = 0;
if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args))
err = -errno;
- if (err == -ENOENT)
+ if (err == expected)
store_all(i915);
errno = 0;
close(i915);
- igt_assert_eq(err, -ENOENT);
+ igt_assert_eq(err, expected);
}
static void
--
2.31.1
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