[PATCH 11/11] Me: Workaround for SLPC and DG1
Matthew Brost
matthew.brost at intel.com
Sun Aug 8 03:23:03 UTC 2021
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 9b52cae16ebb..2817bc46c9de 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -543,10 +543,16 @@ static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ struct intel_gt *gt = slpc_to_gt(slpc);
int ret;
GEM_BUG_ON(!slpc->vma);
+ if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_A0))
+ intel_uncore_write(gt->uncore, _MMIO(0x130050),
+ intel_uncore_read(gt->uncore,
+ GEN6_RP_STATE_CAP));
+
slpc_shared_data_reset(slpc->vaddr);
ret = slpc_reset(slpc);
--
2.28.0
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