[PATCH 32/75] drm/i915: Move scheduler flags
Chris Wilson
chris at chris-wilson.co.uk
Tue Feb 2 11:37:49 UTC 2021
Start extracting the scheduling flags from the engine. We begin with its
own existence.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 6 ++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 19 ++++-------
drivers/gpu/drm/i915/gt/intel_engine_user.c | 34 +++++++++++--------
.../drm/i915/gt/intel_execlists_submission.c | 8 ++++-
drivers/gpu/drm/i915/gt/intel_reset.c | 8 +++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +-
drivers/gpu/drm/i915/i915_request.h | 2 +-
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_scheduler.h | 17 ++++++++++
drivers/gpu/drm/i915/i915_scheduler_types.h | 17 ++++++++++
11 files changed, 84 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index c530839627bb..4f0163457aed 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -261,6 +261,12 @@ intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
return READ_ONCE(engine->props.heartbeat_interval_ms);
}
+static inline bool
+intel_engine_has_scheduler(struct intel_engine_cs *engine)
+{
+ return i915_sched_is_active(intel_engine_get_scheduler(engine));
+}
+
static inline void
intel_engine_kick_scheduler(struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f37521cec2a6..bc5ac85093a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1264,6 +1264,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
engine->sanitize(engine);
engine->set_default_submission(engine);
+ i915_sched_enable(intel_engine_get_scheduler(engine));
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 3b9caa221947..d194e02a273a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -441,13 +441,12 @@ struct intel_engine_cs {
#define I915_ENGINE_USING_CMD_PARSER BIT(0)
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_SCHEDULER BIT(2)
-#define I915_ENGINE_HAS_PREEMPTION BIT(3)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
-#define I915_ENGINE_HAS_TIMESLICES BIT(5)
-#define I915_ENGINE_IS_VIRTUAL BIT(6)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
+#define I915_ENGINE_HAS_PREEMPTION BIT(2)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
+#define I915_ENGINE_HAS_TIMESLICES BIT(4)
+#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
unsigned int flags;
/*
@@ -530,12 +529,6 @@ intel_engine_supports_stats(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_SUPPORTS_STATS;
}
-static inline bool
-intel_engine_has_scheduler(const struct intel_engine_cs *engine)
-{
- return engine->flags & I915_ENGINE_HAS_SCHEDULER;
-}
-
static inline bool
intel_engine_has_preemption(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 64eccdf32a22..3d3cdc080c32 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -90,13 +90,18 @@ static void sort_engines(struct drm_i915_private *i915,
static void set_scheduler_caps(struct drm_i915_private *i915)
{
static const struct {
- u8 engine;
- u8 sched;
- } map[] = {
+ u8 flag;
+ u8 cap;
+ } engine_map[] = {
#define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) }
MAP(HAS_PREEMPTION, PREEMPTION),
MAP(HAS_SEMAPHORES, SEMAPHORES),
MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
+#undef MAP
+ }, sched_map[] = {
+#define MAP(x, y) { I915_SCHED_##x, ilog2(I915_SCHEDULER_CAP_##y) }
+ MAP(ACTIVE_BIT, ENABLED),
+ MAP(PRIORITY_BIT, PRIORITY),
#undef MAP
};
struct intel_engine_cs *engine;
@@ -105,20 +110,21 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
enabled = 0;
disabled = 0;
for_each_uabi_engine(engine, i915) { /* all engines must agree! */
+ struct i915_sched *se = intel_engine_get_scheduler(engine);
int i;
- if (intel_engine_has_scheduler(engine))
- enabled |= (I915_SCHEDULER_CAP_ENABLED |
- I915_SCHEDULER_CAP_PRIORITY);
- else
- disabled |= (I915_SCHEDULER_CAP_ENABLED |
- I915_SCHEDULER_CAP_PRIORITY);
-
- for (i = 0; i < ARRAY_SIZE(map); i++) {
- if (engine->flags & BIT(map[i].engine))
- enabled |= BIT(map[i].sched);
+ for (i = 0; i < ARRAY_SIZE(engine_map); i++) {
+ if (engine->flags & BIT(engine_map[i].flag))
+ enabled |= BIT(engine_map[i].cap);
else
- disabled |= BIT(map[i].sched);
+ disabled |= BIT(engine_map[i].cap);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sched_map); i++) {
+ if (se->flags & BIT(sched_map[i].flag))
+ enabled |= BIT(sched_map[i].cap);
+ else
+ disabled |= BIT(sched_map[i].cap);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d77f2bdee32a..c10ec821e805 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2978,7 +2978,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
}
engine->irq_handler = execlists_irq_handler;
- engine->flags |= I915_ENGINE_HAS_SCHEDULER;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915)) {
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
@@ -3048,6 +3047,9 @@ static void init_execlists(struct intel_engine_cs *engine)
engine->sched.show = execlists_show;
tasklet_setup(&engine->sched.tasklet, execlists_submission_tasklet);
+ __set_bit(I915_SCHED_ACTIVE_BIT, &engine->sched.flags);
+ __set_bit(I915_SCHED_PRIORITY_BIT, &engine->sched.flags);
+
timer_setup(&engine->execlists.timer, execlists_timeslice, 0);
timer_setup(&engine->execlists.preempt, execlists_preempt, 0);
@@ -3458,6 +3460,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
unsigned int count)
{
struct virtual_engine *ve;
+ unsigned long sched;
unsigned int n;
int err;
@@ -3516,6 +3519,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
goto err_put;
}
+ sched = ~0U;
for (n = 0; n < count; n++) {
struct intel_engine_cs *sibling = siblings[n];
@@ -3545,6 +3549,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
ve->siblings[ve->num_siblings++] = sibling;
ve->base.mask |= sibling->mask;
+ sched &= sibling->sched.flags;
/*
* All physical engines must be compatible for their emission
@@ -3586,6 +3591,7 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
ve->base.name,
ve->base.mask,
ENGINE_VIRTUAL);
+ ve->base.sched.flags = sched;
ve->base.sched.submit_request = virtual_submit_request;
tasklet_setup(&ve->base.sched.tasklet, virtual_submission_tasklet);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index e5cb92c7d0f8..149bfd9dd7c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -819,8 +819,12 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
__intel_gt_reset(gt, ALL_ENGINES);
- for_each_engine(engine, gt, id)
- engine->sched.submit_request = nop_submit_request;
+ for_each_engine(engine, gt, id) {
+ struct i915_sched *se = intel_engine_get_scheduler(engine);
+
+ i915_sched_disable(se);
+ se->submit_request = nop_submit_request;
+ }
/*
* Make sure no request can slip through without getting completed by
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 6d274e0b7e3b..be553dcc1663 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -614,7 +614,6 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
}
engine->set_default_submission = guc_set_default_submission;
- engine->flags |= I915_ENGINE_HAS_SCHEDULER;
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
/*
@@ -664,6 +663,8 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
GEM_BUG_ON(INTEL_GEN(i915) < 11);
tasklet_setup(&engine->sched.tasklet, guc_submission_tasklet);
+ __set_bit(I915_SCHED_ACTIVE_BIT, &engine->sched.flags);
+ __set_bit(I915_SCHED_PRIORITY_BIT, &engine->sched.flags);
guc_default_vfuncs(engine);
guc_default_irqs(engine);
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 8d9e59e3cdcb..8eea25cb043e 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -626,7 +626,7 @@ i915_request_active_timeline(const struct i915_request *rq)
static inline bool i915_request_use_scheduler(const struct i915_request *rq)
{
- return intel_engine_has_scheduler(rq->engine);
+ return i915_sched_is_active(i915_request_get_scheduler(rq));
}
static inline bool i915_request_is_executing(const struct i915_request *rq)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index ec328086ed23..62a82b401bcb 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -559,7 +559,7 @@ void i915_request_set_priority(struct i915_request *rq, int prio)
if (__i915_request_is_complete(rq))
goto unlock;
- if (!intel_engine_has_scheduler(engine)) {
+ if (!i915_sched_has_priorities(&engine->sched)) {
rq->sched.attr.priority = prio;
goto unlock;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 07d35df698f6..f8501eaffda3 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -71,6 +71,23 @@ bool i915_sched_suspend_request(struct intel_engine_cs *engine,
void i915_sched_resume_request(struct intel_engine_cs *engine,
struct i915_request *rq);
+/*
+ * Control whether the scheduler accepts any more requests. While
+ * disabled all incoming [ready] requests will be dropped and marked
+ * as completed in error (-EIO).
+ * Typically used when the device fails to recover from a GPU hang
+ * and declared wedged.
+ */
+static inline void i915_sched_enable(struct i915_sched *se)
+{
+ set_bit(I915_SCHED_ENABLE_BIT, &se->flags);
+}
+
+static inline void i915_sched_disable(struct i915_sched *se)
+{
+ clear_bit(I915_SCHED_ENABLE_BIT, &se->flags);
+}
+
void __i915_priolist_free(struct i915_priolist *p);
static inline void i915_priolist_free(struct i915_priolist *p)
{
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index e6ce285a7c1a..1fe60e5b3173 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -17,6 +17,12 @@ struct drm_printer;
struct i915_request;
struct intel_context;
+enum {
+ I915_SCHED_ENABLE_BIT = 0,
+ I915_SCHED_ACTIVE_BIT,
+ I915_SCHED_PRIORITY_BIT, /* priority sorting of queue */
+};
+
/**
* struct i915_sched - funnels requests towards hardware
*
@@ -28,6 +34,7 @@ struct intel_context;
struct i915_sched {
spinlock_t lock; /* protects the scheduling lists and queue */
+ unsigned long flags;
unsigned long mask; /* available scheduling channels */
/*
@@ -179,4 +186,14 @@ struct i915_dependency {
&(rq__)->sched.signalers_list, \
signal_link)
+static inline bool i915_sched_is_active(const struct i915_sched *se)
+{
+ return test_bit(I915_SCHED_ACTIVE_BIT, &se->flags);
+}
+
+static inline bool i915_sched_has_priorities(const struct i915_sched *se)
+{
+ return test_bit(I915_SCHED_PRIORITY_BIT, &se->flags);
+}
+
#endif /* _I915_SCHEDULER_TYPES_H_ */
--
2.20.1
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