[PATCH 35/42] drm/i915: Pass engine to engine->emit_bb_start()
Chris Wilson
chris at chris-wilson.co.uk
Tue Feb 9 21:26:21 UTC 2021
Pass the physical engine to the vfuncs as in the future that may not be
directly available from i915_request.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c | 15 ++---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_blt.c | 32 +++++-----
.../drm/i915/gem/selftests/i915_gem_context.c | 21 +++----
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 18 ++++--
drivers/gpu/drm/i915/gt/gen2_engine_cs.h | 15 +++--
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 18 ++++--
drivers/gpu/drm/i915/gt/gen6_engine_cs.h | 18 ++++--
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 60 ++++++++++++-------
drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 24 ++++++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 6 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 4 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 7 ++-
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/selftests/i915_perf.c | 18 +++---
.../gpu/drm/i915/selftests/i915_scheduler.c | 2 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 16 ++---
22 files changed, 190 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 44821d94544f..fb457f854ba0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -157,6 +157,7 @@ static void clear_pages_worker(struct work_struct *work)
{
struct clear_pages_work *w = container_of(work, typeof(*w), work);
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
+ struct intel_engine_cs *engine = w->ce->engine;
struct i915_vma *vma = w->sleeve->vma;
struct i915_gem_ww_ctx ww;
struct i915_request *rq;
@@ -175,7 +176,7 @@ static void clear_pages_worker(struct work_struct *work)
obj->write_domain = 0;
i915_gem_ww_ctx_init(&ww, false);
- intel_engine_pm_get(w->ce->engine);
+ intel_engine_pm_get(engine);
retry:
err = intel_context_pin_ww(w->ce, &ww);
if (err)
@@ -211,15 +212,15 @@ static void clear_pages_worker(struct work_struct *work)
if (err)
goto out_request;
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (unlikely(err))
goto out_request;
}
- err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err)) {
i915_request_set_error_once(rq, err);
@@ -240,7 +241,7 @@ static void clear_pages_worker(struct work_struct *work)
i915_gem_ww_ctx_fini(&ww);
i915_vma_unpin(w->sleeve->vma);
- intel_engine_pm_put(w->ce->engine);
+ intel_engine_pm_put(engine);
if (unlikely(err)) {
dma_fence_set_error(&w->dma, err);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index fe170186dd42..aaf4cfa200fe 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2548,7 +2548,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
* or actually running by checking the breadcrumb.
*/
if (eb->engine->emit_init_breadcrumb) {
- err = eb->engine->emit_init_breadcrumb(eb->request);
+ err = eb->engine->emit_init_breadcrumb(eb->engine, eb->request);
if (err)
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index d6dac21fce0b..a0a68549580e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -147,6 +147,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
struct intel_context *ce,
u32 value)
{
+ struct intel_engine_cs *engine = ce->engine;
struct i915_gem_ww_ctx ww;
struct i915_request *rq;
struct i915_vma *batch;
@@ -158,7 +159,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
return PTR_ERR(vma);
i915_gem_ww_ctx_init(&ww, true);
- intel_engine_pm_get(ce->engine);
+ intel_engine_pm_get(engine);
retry:
err = i915_gem_object_lock(obj, &ww);
if (err)
@@ -194,14 +195,14 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
if (unlikely(err))
goto out_request;
- if (ce->engine->emit_init_breadcrumb)
- err = ce->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb)
+ err = engine->emit_init_breadcrumb(engine, rq);
if (likely(!err))
- err = ce->engine->emit_bb_start(rq,
- batch->node.start,
- batch->node.size,
- 0);
+ err = engine->emit_bb_start(rq,
+ batch->node.start,
+ batch->node.size,
+ 0);
out_request:
if (unlikely(err))
i915_request_set_error_once(rq, err);
@@ -220,7 +221,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj,
goto retry;
}
i915_gem_ww_ctx_fini(&ww);
- intel_engine_pm_put(ce->engine);
+ intel_engine_pm_put(engine);
return err;
}
@@ -354,6 +355,7 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
struct intel_context *ce)
{
struct i915_address_space *vm = ce->vm;
+ struct intel_engine_cs *engine = ce->engine;
struct i915_vma *vma[2], *batch;
struct i915_gem_ww_ctx ww;
struct i915_request *rq;
@@ -368,7 +370,7 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
return PTR_ERR(vma[1]);
i915_gem_ww_ctx_init(&ww, true);
- intel_engine_pm_get(ce->engine);
+ intel_engine_pm_get(engine);
retry:
err = i915_gem_object_lock(src, &ww);
if (!err)
@@ -416,15 +418,15 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
goto out_request;
}
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (unlikely(err))
goto out_request;
}
- err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
out_request:
if (unlikely(err))
@@ -446,7 +448,7 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src,
goto retry;
}
i915_gem_ww_ctx_fini(&ww);
- intel_engine_pm_put(ce->engine);
+ intel_engine_pm_put(engine);
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 1ecd362b131a..14f7fd294674 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -923,6 +923,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
struct i915_request **rq_out)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
struct i915_gem_ww_ctx ww;
struct i915_vma *batch;
@@ -930,7 +931,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
struct drm_i915_gem_object *rpcs;
int err;
- GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
+ GEM_BUG_ON(!intel_engine_can_store_dword(engine));
if (INTEL_GEN(i915) < 8)
return -EINVAL;
@@ -985,15 +986,15 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
if (err)
goto skip_request;
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto skip_request;
}
- err = rq->engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- 0);
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
if (err)
goto skip_request;
@@ -1555,8 +1556,8 @@ static int write_to_scratch(struct i915_gem_context *ctx,
if (err)
goto skip_request;
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto skip_request;
}
@@ -1693,8 +1694,8 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (err)
goto skip_request;
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto skip_request;
}
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index b3fff7a955f2..3f5cebf2d233 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -139,10 +139,11 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
return 0;
}
-static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
+static u32 *__gen2_emit_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *rq, u32 *cs,
int flush, int post)
{
- GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
+ GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
*cs++ = MI_FLUSH;
@@ -167,9 +168,11 @@ static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
return cs;
}
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
+u32 *gen3_emit_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
- return __gen2_emit_breadcrumb(rq, cs, 16, 8);
+ return __gen2_emit_breadcrumb(engine, rq, cs, 16, 8);
}
static u32 *__gen4_emit_breadcrumb(struct i915_request *rq, u32 *cs,
@@ -213,12 +216,15 @@ static u32 *__gen4_emit_breadcrumb(struct i915_request *rq, u32 *cs,
return cs;
}
-u32 *gen4_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
+u32 *gen4_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
return __gen4_emit_breadcrumb(rq, cs, 8, 8);
}
-int gen4_emit_init_breadcrumb_xcs(struct i915_request *rq)
+int gen4_emit_init_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq)
{
struct intel_timeline *tl = i915_request_timeline(rq);
u32 *cs;
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
index ba7567b15229..99cc752c25b6 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h
@@ -15,11 +15,18 @@ int gen2_emit_flush(struct i915_request *rq, u32 mode);
int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode);
int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode);
-u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs);
-u32 *gen4_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
+u32 *gen3_emit_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen4_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
-u32 *gen4_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
-int gen4_emit_init_breadcrumb_xcs(struct i915_request *rq);
+u32 *gen4_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+int gen4_emit_init_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq);
int i830_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
index 14cab4c726ce..080aaa2bcfc9 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
@@ -139,7 +139,9 @@ int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode)
return 0;
}
-u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
+u32 *gen6_emit_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
@@ -155,7 +157,7 @@ u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
*cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = PIPE_CONTROL_QW_WRITE;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ *cs++ = intel_gt_scratch_offset(engine->gt,
INTEL_GT_SCRATCH_FIELD_DEFAULT) |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
@@ -362,7 +364,9 @@ int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode)
return 0;
}
-u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
+u32 *gen7_emit_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
@@ -397,7 +401,9 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
return cs;
}
-u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
+u32 *gen6_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
@@ -425,7 +431,9 @@ u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
}
#define GEN7_XCS_WA 32
-u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
+u32 *gen7_emit_breadcrumb_xcs(const struct intel_engine_cs *engien,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.h b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h
index 76c6bc9f3bde..75baea303dd0 100644
--- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h
@@ -16,12 +16,22 @@ struct intel_engine_cs;
int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode);
int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode);
int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode);
-u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
-u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
+
+u32 *gen6_emit_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen6_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode);
-u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
-u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
+
+u32 *gen7_emit_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen7_emit_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
int gen6_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 4a0d32584ef0..8a446dad32f5 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -330,13 +330,14 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
return 0;
}
-static u32 preempt_address(struct intel_engine_cs *engine)
+static u32 preempt_address(const struct intel_engine_cs *engine)
{
return (i915_ggtt_offset(engine->status_page.vma) +
I915_GEM_HWS_PREEMPT_ADDR);
}
-int gen8_emit_init_breadcrumb(struct i915_request *rq)
+int gen8_emit_init_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *rq)
{
u32 *cs;
@@ -473,7 +474,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *rq, u32 *cs)
return cs;
}
-static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)
+static u32 *emit_preempt_busywait(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
*cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
*cs++ = MI_SEMAPHORE_WAIT |
@@ -481,7 +484,7 @@ static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = preempt_address(rq->engine);
+ *cs++ = preempt_address(engine);
*cs++ = 0;
*cs++ = MI_NOOP;
@@ -489,13 +492,15 @@ static u32 *emit_preempt_busywait(struct i915_request *rq, u32 *cs)
}
static __always_inline u32*
-gen8_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
+gen8_emit_fini_breadcrumb_tail(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
if (i915_request_use_busywait(rq))
- cs = emit_preempt_busywait(rq, cs);
+ cs = emit_preempt_busywait(engine, rq, cs);
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
@@ -520,12 +525,17 @@ static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
return __gen8_emit_flush_dw(cs, rq->fence.seqno, offset, flags);
}
-u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
+u32 *gen8_emit_fini_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
- return gen8_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
+ return gen8_emit_fini_breadcrumb_tail(engine, rq,
+ emit_xcs_breadcrumb(rq, cs));
}
-u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
+u32 *gen8_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
unsigned int flags = PIPE_CONTROL_FLUSH_ENABLE | PIPE_CONTROL_CS_STALL;
@@ -548,10 +558,12 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
- return gen8_emit_fini_breadcrumb_tail(rq, cs);
+ return gen8_emit_fini_breadcrumb_tail(engine, rq, cs);
}
-u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
+u32 *gen11_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
@@ -574,7 +586,7 @@ u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset, 0, flags);
- return gen8_emit_fini_breadcrumb_tail(rq, cs);
+ return gen8_emit_fini_breadcrumb_tail(engine, rq, cs);
}
/*
@@ -596,7 +608,9 @@ u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
* used by the instructions is not pre-fetched.
*/
-static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
+static u32 *gen12_emit_preempt_busywait(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
*cs++ = MI_ARB_CHECK; /* trigger IDLE->ACTIVE first */
*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
@@ -604,7 +618,7 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
MI_SEMAPHORE_POLL |
MI_SEMAPHORE_SAD_EQ_SDD;
*cs++ = 0;
- *cs++ = preempt_address(rq->engine);
+ *cs++ = preempt_address(engine);
*cs++ = 0;
*cs++ = 0;
@@ -612,13 +626,15 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
}
static __always_inline u32*
-gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
+gen12_emit_fini_breadcrumb_tail(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
if (i915_request_use_busywait(rq))
- cs = gen12_emit_preempt_busywait(rq, cs);
+ cs = gen12_emit_preempt_busywait(engine, rq, cs);
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
@@ -626,14 +642,18 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
return gen8_emit_wa_tail(rq, cs);
}
-u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
+u32 *gen12_emit_fini_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
/* XXX Stalling flush before seqno write; post-sync not */
cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
- return gen12_emit_fini_breadcrumb_tail(rq, cs);
+ return gen12_emit_fini_breadcrumb_tail(engine, rq, cs);
}
-u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
+u32 *gen12_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs)
{
struct intel_timeline *tl = rcu_dereference_protected(rq->timeline, 1);
u32 offset = __i915_request_hwsp_offset(rq);
@@ -660,5 +680,5 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
cs = __gen8_emit_write_rcs(cs, rq->fence.seqno, offset,
PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags);
- return gen12_emit_fini_breadcrumb_tail(rq, cs);
+ return gen12_emit_fini_breadcrumb_tail(engine, rq, cs);
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
index cc6e21d3662a..be4f84670d34 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h
@@ -14,6 +14,7 @@
#include "intel_gpu_commands.h"
struct i915_request;
+struct intel_engine_cs;
int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);
@@ -22,7 +23,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);
int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);
int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);
-int gen8_emit_init_breadcrumb(struct i915_request *rq);
+int gen8_emit_init_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *rq);
int gen8_emit_bb_start_noarb(struct i915_request *rq,
u64 offset, u32 len,
@@ -31,12 +33,22 @@ int gen8_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
const unsigned int flags);
-u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
-u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
+u32 *gen8_emit_fini_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen12_emit_fini_breadcrumb_xcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
-u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
-u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
-u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
+u32 *gen8_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen11_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
+u32 *gen12_emit_fini_breadcrumb_rcs(const struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ u32 *cs);
static inline u32 *
__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1846230dd8bd..0608dbb149ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -759,7 +759,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
mutex_lock(&ce->timeline->mutex);
spin_lock_irq(&se->lock);
- dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
+ dw = engine->emit_fini_breadcrumb(engine, &frame->rq, frame->cs) -
+ frame->cs;
spin_unlock_irq(&se->lock);
mutex_unlock(&ce->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6a1491dbebd2..f0107f9fd356 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -396,8 +396,10 @@ struct intel_engine_cs {
unsigned int dispatch_flags);
#define I915_DISPATCH_SECURE BIT(0)
#define I915_DISPATCH_PINNED BIT(1)
- int (*emit_init_breadcrumb)(struct i915_request *rq);
- u32 *(*emit_fini_breadcrumb)(struct i915_request *rq,
+ int (*emit_init_breadcrumb)(const struct intel_engine_cs *engine,
+ struct i915_request *rq);
+ u32 *(*emit_fini_breadcrumb)(const struct intel_engine_cs *engien,
+ struct i915_request *rq,
u32 *cs);
unsigned int emit_fini_breadcrumb_dw;
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 6e57b5f93138..4654188f3b73 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -193,7 +193,9 @@ static int mock_emit_flush(struct i915_request *request, unsigned int flags)
return 0;
}
-static u32 *mock_emit_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *mock_emit_breadcrumb(const struct intel_engine_cs *engine,
+ struct i915_request *request,
+ u32 *cs)
{
return cs;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 080142c86339..e90d0f4fef15 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -713,8 +713,8 @@ static int live_error_interrupt(void *arg)
goto out;
}
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err) {
i915_request_add(rq);
goto out;
@@ -850,8 +850,8 @@ semaphore_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx)
goto out_ce;
err = 0;
- if (rq->engine->emit_init_breadcrumb)
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb)
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err == 0)
err = emit_semaphore_chain(rq, vma, idx);
if (err == 0)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 5323fd56efd6..ea05892a4d94 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -236,8 +236,8 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_BATCH_BUFFER_END; /* not reached */
intel_gt_chipset_flush(engine->gt);
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto cancel_rq;
}
@@ -246,7 +246,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
if (INTEL_GEN(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
- err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
+ err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
cancel_rq:
if (err) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index e5ee6136c81f..6f09716ce75c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -561,7 +561,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
}
if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
- err = engine->emit_init_breadcrumb(rq);
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto err_request;
}
@@ -851,7 +851,7 @@ static int scrub_whitelisted_registers(struct intel_context *ce)
}
if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
- err = engine->emit_init_breadcrumb(rq);
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto err_request;
}
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 43f31c2eab14..4167eeaf65f4 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -360,11 +360,12 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
{
struct intel_vgpu *vgpu = workload->vgpu;
struct i915_request *req = workload->req;
+ struct intel_engine_cs *engine = req->context->engine;
void *shadow_ring_buffer_va;
u32 *cs;
int err;
- if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context))
+ if (IS_GEN(engine->i915, 9) && is_inhibit_context(req->context))
intel_vgpu_restore_inhibit_context(vgpu, req);
/*
@@ -377,8 +378,8 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
* requests from gvt always set the has_init_breadcrumb flag, here
* need to do the emit_init_breadcrumb for all the requests.
*/
- if (req->engine->emit_init_breadcrumb) {
- err = req->engine->emit_init_breadcrumb(req);
+ if (engine->emit_init_breadcrumb) {
+ err = engine->emit_init_breadcrumb(engine, req);
if (err) {
gvt_vgpu_err("fail to emit init breadcrumb\n");
return err;
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 72019ba4907d..e0ebdefd35ee 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -518,7 +518,7 @@ bool __i915_request_submit(struct i915_request *request)
i915_sw_fence_signaled(&request->semaphore))
request->context->saturated |= request->sched.semaphores;
- engine->emit_fini_breadcrumb(request,
+ engine->emit_fini_breadcrumb(engine, request,
request->ring->vaddr + request->postfix);
trace_i915_request_execute(request);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index c1adea8765a9..401ee975bbe2 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1753,6 +1753,7 @@ static int context_sync(struct intel_context *ce)
static struct i915_request *
submit_batch(struct intel_context *ce, u64 addr)
{
+ struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
int err;
@@ -1761,10 +1762,10 @@ submit_batch(struct intel_context *ce, u64 addr)
return rq;
err = 0;
- if (rq->engine->emit_init_breadcrumb) /* detect a hang */
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (engine->emit_init_breadcrumb) /* detect a hang */
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err == 0)
- err = rq->engine->emit_bb_start(rq, addr, 0, 0);
+ err = engine->emit_bb_start(rq, addr, 0, 0);
if (err == 0)
i915_request_get(rq);
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index e9d86dab8677..56bb7db79c23 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -221,8 +221,8 @@ static int live_noa_delay(void *arg)
goto out;
}
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (stream->engine->emit_init_breadcrumb) {
+ err = stream->engine->emit_init_breadcrumb(stream->engine, rq);
if (err) {
i915_request_add(rq);
goto out;
@@ -317,8 +317,8 @@ static int live_noa_gpr(void *arg)
}
i915_request_get(rq);
- if (rq->engine->emit_init_breadcrumb) {
- err = rq->engine->emit_init_breadcrumb(rq);
+ if (stream->engine->emit_init_breadcrumb) {
+ err = stream->engine->emit_init_breadcrumb(stream->engine, rq);
if (err) {
i915_request_add(rq);
goto out_rq;
@@ -342,16 +342,16 @@ static int live_noa_gpr(void *arg)
intel_ring_advance(rq, cs);
/* Execute the GPU delay */
- err = rq->engine->emit_bb_start(rq,
- i915_ggtt_offset(stream->noa_wait), 0,
- I915_DISPATCH_SECURE);
+ err = stream->engine->emit_bb_start(rq,
+ i915_ggtt_offset(stream->noa_wait), 0,
+ I915_DISPATCH_SECURE);
if (err) {
i915_request_add(rq);
goto out_rq;
}
/* Read the GPR back, using the pinned global HWSP for convenience */
- store = memset32(rq->engine->status_page.addr + 512, 0, 32);
+ store = memset32(stream->engine->status_page.addr + 512, 0, 32);
for (i = 0; i < 32; i++) {
u32 cmd;
@@ -369,7 +369,7 @@ static int live_noa_gpr(void *arg)
*cs++ = cmd;
*cs++ = gpr0 + i * sizeof(u32);
- *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +
+ *cs++ = i915_ggtt_offset(stream->engine->status_page.vma) +
offset_in_page(store) +
i * sizeof(u32);
*cs++ = 0;
diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
index 59df7f834dad..e0265c303120 100644
--- a/drivers/gpu/drm/i915/selftests/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c
@@ -684,7 +684,7 @@ __write_timestamp(struct intel_engine_cs *engine,
}
if (engine->emit_init_breadcrumb) {
- err = engine->emit_init_breadcrumb(rq);
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto out_request;
}
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 0e6c1ea0082a..7e148e3975cc 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -135,15 +135,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
batch = spin->batch;
- if (INTEL_GEN(rq->engine->i915) >= 8) {
+ if (INTEL_GEN(engine->i915) >= 8) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = upper_32_bits(hws_address(hws, rq));
- } else if (INTEL_GEN(rq->engine->i915) >= 6) {
+ } else if (INTEL_GEN(engine->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
- } else if (INTEL_GEN(rq->engine->i915) >= 4) {
+ } else if (INTEL_GEN(engine->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
@@ -155,11 +155,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = arbitration_command;
- if (INTEL_GEN(rq->engine->i915) >= 8)
+ if (INTEL_GEN(engine->i915) >= 8)
*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
- else if (IS_HASWELL(rq->engine->i915))
+ else if (IS_HASWELL(engine->i915))
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
- else if (INTEL_GEN(rq->engine->i915) >= 6)
+ else if (INTEL_GEN(engine->i915) >= 6)
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
@@ -171,13 +171,13 @@ igt_spinner_create_request(struct igt_spinner *spin,
intel_gt_chipset_flush(engine->gt);
if (engine->emit_init_breadcrumb) {
- err = engine->emit_init_breadcrumb(rq);
+ err = engine->emit_init_breadcrumb(engine, rq);
if (err)
goto cancel_rq;
}
flags = 0;
- if (INTEL_GEN(rq->engine->i915) <= 5)
+ if (INTEL_GEN(engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
--
2.20.1
More information about the Intel-gfx-trybot
mailing list