[PATCH 2/7] dbg
Chris Wilson
chris at chris-wilson.co.uk
Fri Feb 12 13:27:32 UTC 2021
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index f75f6751cf3f..cd8abec4ccdf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -371,25 +371,41 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
const u64 start = i915_vma_offset(vma);
const u64 size = i915_vma_size(vma);
- if (size < entry->pad_to_size)
+ if (size < entry->pad_to_size) {
+ GEM_TRACE("vma [%llx, %llx] too small < %lld\n",
+ start, size, entry->pad_to_size);
return true;
+ }
- if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
+ if (entry->alignment && !IS_ALIGNED(start, entry->alignment)) {
+ GEM_TRACE("vma [%llx, %llx] misaligned %llx\n",
+ start, size, entry->alignment);
return true;
+ }
- if (flags & EXEC_OBJECT_PINNED && start != entry->offset)
+ if (flags & EXEC_OBJECT_PINNED && start != entry->offset) {
+ GEM_TRACE("vma [%llx, %llx] pinned != %llx\n",
+ start, size, entry->offset);
return true;
+ }
- if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS)
+ if (flags & __EXEC_OBJECT_NEEDS_BIAS && start < BATCH_OFFSET_BIAS) {
+ GEM_TRACE("vma [%llx, %llx] bias < %x\n",
+ start, size, BATCH_OFFSET_BIAS);
return true;
+ }
if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
- (start + size + 4095) >> 32)
+ (start + size + 4095) >> 32) {
+ GEM_TRACE("vma [%llx, %llx] !48b\n", start, size);
return true;
+ }
if (flags & __EXEC_OBJECT_NEEDS_MAP &&
- !i915_vma_is_map_and_fenceable(vma))
+ !i915_vma_is_map_and_fenceable(vma)) {
+ GEM_TRACE("vma [%llx, %llx] unfenced\n", start, size);
return true;
+ }
return false;
}
--
2.20.1
More information about the Intel-gfx-trybot
mailing list