[PATCH 52/53] drm/i915/gt: Implement ring scheduler for gen4/5

[Chris Wilson]

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 .../gpu/drm/i915/gt/intel_ring_scheduler.c    | 45 ++++++++++++++-----
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
index e3503967e52e..b133fa6611bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c
@@ -1006,8 +1006,16 @@ static void ring_release(struct intel_engine_cs *engine)
 
 static void setup_irq(struct intel_engine_cs *engine)
 {
-	engine->irq_enable = gen6_irq_enable;
-	engine->irq_disable = gen6_irq_disable;
+	if (INTEL_GEN(engine->i915) >= 6) {
+		engine->irq_enable = gen6_irq_enable;
+		engine->irq_disable = gen6_irq_disable;
+	} else if (INTEL_GEN(engine->i915) >= 5) {
+		engine->irq_enable = gen5_irq_enable;
+		engine->irq_disable = gen5_irq_disable;
+	} else {
+		engine->irq_enable = gen3_irq_enable;
+		engine->irq_disable = gen3_irq_disable;
+	}
 }
 
 static void setup_common(struct intel_engine_cs *engine)
@@ -1039,12 +1047,17 @@ static void setup_common(struct intel_engine_cs *engine)
 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
 	else if (INTEL_GEN(i915) >= 6)
 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
+	else if (INTEL_GEN(i915) >= 5)
+		engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
 	else
 		engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
 
-	engine->set_default_submission = set_default_submission;
+	if (INTEL_GEN(i915) >= 6)
+		engine->emit_bb_start = gen6_emit_bb_start;
+	else
+		engine->emit_bb_start = gen4_emit_bb_start;
 
-	engine->emit_bb_start = gen6_emit_bb_start;
+	engine->set_default_submission = set_default_submission;
 }
 
 static void setup_rcs(struct intel_engine_cs *engine)
@@ -1061,19 +1074,31 @@ static void setup_rcs(struct intel_engine_cs *engine)
 		engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
 		if (IS_HASWELL(i915))
 			engine->emit_bb_start = hsw_emit_bb_start;
-	} else {
+	} else if (INTEL_GEN(i915) >= 6) {
 		engine->emit_flush = gen6_emit_flush_rcs;
 		engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
+	} else if (INTEL_GEN(i915) >= 5) {
+		engine->emit_flush = gen4_emit_flush_rcs;
+	} else {
+		engine->emit_flush = gen4_emit_flush_rcs;
+		engine->irq_enable_mask = I915_USER_INTERRUPT;
 	}
 }
 
 static void setup_vcs(struct intel_engine_cs *engine)
 {
-	engine->emit_flush = gen6_emit_flush_vcs;
-	engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
-
-	if (IS_GEN(engine->i915, 6))
-		engine->fw_domain = FORCEWAKE_ALL;
+	if (INTEL_GEN(engine->i915) >= 6) {
+		if (IS_GEN(engine->i915, 6))
+			engine->fw_domain = FORCEWAKE_ALL;
+		engine->emit_flush = gen6_emit_flush_vcs;
+		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+	} else if (INTEL_GEN(engine->i915) >= 5) {
+		engine->emit_flush = gen4_emit_flush_vcs;
+		engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
+	} else {
+		engine->emit_flush = gen4_emit_flush_vcs;
+		engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
+	}
 }
 
 static void setup_bcs(struct intel_engine_cs *engine)
-- 
2.20.1