[PATCH] drm/i915: Fix the 12 BPC bits for PIPE_MISC reg

[Nautiyal, Ankit K]

From: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

Till GEN 12 the PIPE_MISC bits 5-7 are used to set the dithering BPC,
with valid values of 6, 8, 10 BPC. For newer platforms these bits
are used for getting the port output bpc, with valid values of:
6, 8, 10, 12 BPC, and need to be programmed whether dithering is
enabled or not.

This patch:
-corrects the bits 5-7 for PIPE MISC register for 12 BPC.
-avoids writing 12 BPC for platforms <= GEN 12.
-renames the bits and mask to to avoid confusion with dithering bpc.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
 drivers/gpu/drm/i915/i915_reg.h              | 4 ++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d038fa6..ae5e5aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5795,7 +5795,8 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 		val |= PIPEMISC_DITHER_10_BPC;
 		break;
 	case 36:
-		val |= PIPEMISC_DITHER_12_BPC;
+		if (DISPLAY_VER(dev_priv) > 12)
+			val |= PIPEMISC_PORT_OUTPUT_12_BPC;
 		break;
 	default:
 		MISSING_CASE(crtc_state->pipe_bpp);
@@ -5848,15 +5849,15 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
 
 	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
 
-	switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
+	switch (tmp & PIPEMISC_BPC_MASK) {
 	case PIPEMISC_DITHER_6_BPC:
 		return 18;
 	case PIPEMISC_DITHER_8_BPC:
 		return 24;
 	case PIPEMISC_DITHER_10_BPC:
 		return 30;
-	case PIPEMISC_DITHER_12_BPC:
-		return 36;
+	case PIPEMISC_PORT_OUTPUT_12_BPC:
+		return DISPLAY_VER(dev_priv) > 12 ? 36 : 0;
 	default:
 		MISSING_CASE(tmp);
 		return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34d3806..323fe67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6260,11 +6260,11 @@ enum {
 #define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */
 #define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)
 #define   PIPEMISC_PIXEL_ROUNDING_TRUNC	REG_BIT(8) /* tgl+ */
-#define   PIPEMISC_DITHER_BPC_MASK	(7 << 5)
+#define   PIPEMISC_BPC_MASK		(7 << 5)
 #define   PIPEMISC_DITHER_8_BPC		(0 << 5)
 #define   PIPEMISC_DITHER_10_BPC	(1 << 5)
 #define   PIPEMISC_DITHER_6_BPC		(2 << 5)
-#define   PIPEMISC_DITHER_12_BPC	(3 << 5)
+#define   PIPEMISC_PORT_OUTPUT_12_BPC	(4 << 5) /* adl+ */
 #define   PIPEMISC_DITHER_ENABLE	(1 << 4)
 #define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)
 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
-- 
2.8.1