[PATCH i-g-t v21 35/35] tests/gem_linear_blits: Use intel allocator

Zbigniew Kempczyński zbigniew.kempczynski at intel.com
Mon Mar 1 09:34:51 UTC 2021


From: Dominik Grzegorzek <dominik.grzegorzek at intel.com>

Use intel allocator directly, without intel-bb infrastructure.

v2: for relocations suggests use incremented offsets  instead of 0.

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek at intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
---
 tests/i915/gem_linear_blits.c | 117 +++++++++++++++++++++++++---------
 1 file changed, 87 insertions(+), 30 deletions(-)

diff --git a/tests/i915/gem_linear_blits.c b/tests/i915/gem_linear_blits.c
index cae42d52a..d351463fc 100644
--- a/tests/i915/gem_linear_blits.c
+++ b/tests/i915/gem_linear_blits.c
@@ -56,7 +56,8 @@ IGT_TEST_DESCRIPTION("Test doing many blits with a working set larger than the"
 static uint32_t linear[WIDTH*HEIGHT];
 
 static void
-copy(int fd, uint32_t dst, uint32_t src)
+copy(int fd, uint64_t ahnd, uint32_t dst, uint32_t src,
+     uint64_t dst_offset, uint64_t src_offset, bool do_relocs)
 {
 	uint32_t batch[12];
 	struct drm_i915_gem_relocation_entry reloc[2];
@@ -77,41 +78,58 @@ copy(int fd, uint32_t dst, uint32_t src)
 		  WIDTH*4;
 	batch[i++] = 0; /* dst x1,y1 */
 	batch[i++] = (HEIGHT << 16) | WIDTH; /* dst x2,y2 */
-	batch[i++] = 0; /* dst reloc */
+	batch[i++] = dst_offset;
 	if (intel_gen(intel_get_drm_devid(fd)) >= 8)
-		batch[i++] = 0;
+		batch[i++] = dst_offset >> 32;
 	batch[i++] = 0; /* src x1,y1 */
 	batch[i++] = WIDTH*4;
-	batch[i++] = 0; /* src reloc */
+	batch[i++] = src_offset;
 	if (intel_gen(intel_get_drm_devid(fd)) >= 8)
-		batch[i++] = 0;
+		batch[i++] = src_offset >> 32;
 	batch[i++] = MI_BATCH_BUFFER_END;
 	batch[i++] = MI_NOOP;
 
-	memset(reloc, 0, sizeof(reloc));
-	reloc[0].target_handle = dst;
-	reloc[0].delta = 0;
-	reloc[0].offset = 4 * sizeof(batch[0]);
-	reloc[0].presumed_offset = 0;
-	reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
-	reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
-
-	reloc[1].target_handle = src;
-	reloc[1].delta = 0;
-	reloc[1].offset = 7 * sizeof(batch[0]);
-	if (intel_gen(intel_get_drm_devid(fd)) >= 8)
-		reloc[1].offset += sizeof(batch[0]);
-	reloc[1].presumed_offset = 0;
-	reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
-	reloc[1].write_domain = 0;
-
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = dst;
 	obj[1].handle = src;
 	obj[2].handle = gem_create(fd, 4096);
 	gem_write(fd, obj[2].handle, 0, batch, i * sizeof(batch[0]));
-	obj[2].relocation_count = 2;
-	obj[2].relocs_ptr = to_user_pointer(reloc);
+
+	if (do_relocs) {
+		memset(reloc, 0, sizeof(reloc));
+		reloc[0].target_handle = dst;
+		reloc[0].delta = 0;
+		reloc[0].offset = 4 * sizeof(batch[0]);
+		reloc[0].presumed_offset = dst_offset;
+		reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
+		reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
+
+		reloc[1].target_handle = src;
+		reloc[1].delta = 0;
+		reloc[1].offset = 7 * sizeof(batch[0]);
+		if (intel_gen(intel_get_drm_devid(fd)) >= 8)
+			reloc[1].offset += sizeof(batch[0]);
+		reloc[1].presumed_offset = src_offset;
+		reloc[1].read_domains = I915_GEM_DOMAIN_RENDER;
+		reloc[1].write_domain = 0;
+
+		obj[2].relocation_count = 2;
+		obj[2].relocs_ptr = to_user_pointer(reloc);
+	} else {
+		obj[0].offset = CANONICAL(dst_offset);
+		obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+		obj[1].offset = CANONICAL(src_offset);
+		obj[1].flags = EXEC_OBJECT_PINNED |
+			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+		obj[2].offset = intel_allocator_alloc(ahnd, obj[2].handle,
+						      sizeof(linear), 0);
+		obj[2].offset = CANONICAL(obj[2].offset);
+		obj[2].flags = EXEC_OBJECT_PINNED |
+			       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	}
 
 	memset(&exec, 0, sizeof(exec));
 	exec.buffers_ptr = to_user_pointer(obj);
@@ -120,6 +138,9 @@ copy(int fd, uint32_t dst, uint32_t src)
 	exec.flags = gem_has_blt(fd) ? I915_EXEC_BLT : 0;
 
 	gem_execbuf(fd, &exec);
+
+	if (!do_relocs)
+		intel_allocator_free(ahnd, obj[2].handle);
 	gem_close(fd, obj[2].handle);
 }
 
@@ -157,17 +178,38 @@ check_bo(int fd, uint32_t handle, uint32_t val)
 	igt_assert_eq(num_errors, 0);
 }
 
-static void run_test(int fd, int count)
+/* We don't have alignment detection yet, so assume worst scenario */
+#define ALIGNMENT (2048*1024)
+static void run_test(int fd, int count, bool do_relocs)
 {
 	uint32_t *handle, *start_val;
+	uint64_t *offset, ahnd, gtt_size, address = 0;
 	uint32_t start = 0;
 	int i;
 
+	if (!do_relocs) {
+		ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+	} else {
+		gtt_size = gem_aperture_size(fd);
+		if ((gtt_size - 1) >> 32)
+			gtt_size = 1ULL << 32;
+	}
+
 	handle = malloc(sizeof(uint32_t) * count * 2);
 	start_val = handle + count;
+	offset = calloc(1, sizeof(uint64_t) * count);
 
 	for (i = 0; i < count; i++) {
 		handle[i] = create_bo(fd, start);
+
+		if (!do_relocs) {
+			offset[i] = intel_allocator_alloc(ahnd, handle[i],
+							  sizeof(linear), 4096);
+		} else {
+			offset[i] = address % gtt_size;
+			address = ALIGN(address + sizeof(linear), ALIGNMENT);
+		}
+
 		start_val[i] = start;
 		start += 1024 * 1024 / 4;
 	}
@@ -178,17 +220,23 @@ static void run_test(int fd, int count)
 
 		if (src == dst)
 			continue;
+		copy(fd, ahnd, handle[dst], handle[src],
+		     offset[dst], offset[src], do_relocs);
 
-		copy(fd, handle[dst], handle[src]);
 		start_val[dst] = start_val[src];
 	}
 
 	for (i = 0; i < count; i++) {
 		check_bo(fd, handle[i], start_val[i]);
+		if (!do_relocs)
+			intel_allocator_free(ahnd, handle[i]);
 		gem_close(fd, handle[i]);
 	}
 
 	free(handle);
+
+	if (!do_relocs)
+		intel_allocator_close(ahnd);
 }
 
 #define MAX_32b ((1ull << 32) - 4096)
@@ -197,38 +245,47 @@ igt_main
 {
 	const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
 	uint64_t count = 0;
+	bool do_relocs;
 	int fd = -1;
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 		gem_require_blitter(fd);
+		do_relocs = !gem_uses_ppgtt(fd);
 
 		count = gem_aperture_size(fd);
 		if (count >> 32)
 			count = MAX_32b;
+		else
+			do_relocs = true;
+
 		count = 3 + count / (1024*1024);
 		igt_require(count > 1);
 		intel_require_memory(count, sizeof(linear), CHECK_RAM);
-
 		igt_debug("Using %'"PRIu64" 1MiB buffers\n", count);
 		count = (count + ncpus - 1) / ncpus;
 	}
 
 	igt_subtest("basic")
-		run_test(fd, 2);
+		run_test(fd, 2, do_relocs);
 
 	igt_subtest("normal") {
+		intel_allocator_multiprocess_start();
+		do_relocs = true;
 		igt_fork(child, ncpus)
-			run_test(fd, count);
+			run_test(fd, count, do_relocs);
 		igt_waitchildren();
+		intel_allocator_multiprocess_stop();
 	}
 
 	igt_subtest("interruptible") {
+		intel_allocator_multiprocess_start();
 		igt_fork_signal_helper();
 		igt_fork(child, ncpus)
-			run_test(fd, count);
+			run_test(fd, count, do_relocs);
 		igt_waitchildren();
 		igt_stop_signal_helper();
+		intel_allocator_multiprocess_stop();
 	}
 }
-- 
2.26.0



More information about the Intel-gfx-trybot mailing list