[PATCH 4/4] drm/i915/display: Test intel_psr_puase/resume on set_cdclk

[Gwan-gyeong Mun]

do not merge this commit.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a9019287f7d5..766f90eb133f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
 #include "intel_cdclk.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_psr.h"
 
 /**
  * DOC: CDCLK / RAWCLK
@@ -1553,6 +1554,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  enum pipe pipe)
 {
 	int cdclk = cdclk_config->cdclk;
+	struct intel_encoder *encoder;
 	int vco = cdclk_config->vco;
 	u32 val, divider;
 	int ret;
@@ -1605,6 +1607,15 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		break;
 	}
 
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		if (intel_dp->psr.pipe != pipe)
+			continue;
+
+		intel_psr_pause(intel_dp);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 10) {
 		if (dev_priv->cdclk.hw.vco != 0 &&
 		    dev_priv->cdclk.hw.vco != vco)
@@ -1633,6 +1644,15 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
 	intel_de_write(dev_priv, CDCLK_CTL, val);
 
+	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
+		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+		if (intel_dp->psr.pipe != pipe)
+			continue;
+
+		intel_psr_resume(intel_dp);
+	}
+
 	if (pipe != INVALID_PIPE)
 		intel_wait_for_vblank(dev_priv, pipe);
 
-- 
2.30.1