[PATCH] ffs

[Chris Wilson]

---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3b4a7da60f0b..4f617500d6d7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -881,6 +881,8 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 static void
 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
+	wa_init_mcr(i915, wal);
+
 	/* WaDisableKillLogic:bxt,skl,kbl */
 	if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
 		wa_write_or(wal,
@@ -983,7 +985,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	unsigned int slice, subslice;
 	u32 l3_en, mcr, mcr_mask;
 
-	GEM_BUG_ON(INTEL_GEN(i915) < 10);
+	GEM_BUG_ON(INTEL_GEN(i915) < 9);
 
 	/*
 	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
@@ -1024,13 +1026,13 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		l3_en = ~0;
 	}
 
-	slice = fls(sseu->slice_mask) - 1;
-	subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
+	slice = ffs(sseu->slice_mask) - 1;
+	subslice = ffs(l3_en & intel_sseu_get_subslices(sseu, slice));
 	if (!subslice) {
 		drm_warn(&i915->drm,
 			 "No common index found between subslice mask %x and L3 bank mask %x!\n",
 			 intel_sseu_get_subslices(sseu, slice), l3_en);
-		subslice = fls(l3_en);
+		subslice = ffs(l3_en);
 		drm_WARN_ON(&i915->drm, !subslice);
 	}
 	subslice--;
-- 
2.20.1