[PATCH] drm/i915: Bump up CDCLK for ADL

[Stanislav Lisovskiy]

Bumping up CDCLK often helps in case of FIFO underruns.
This is a temprorary solution(we have that for TGL still though),
because there is a suspicion that we simply miscalculate required
CDCLK for plane downscaling case, which has higher display buffer
bandwidth requirements.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 978af9764623..ac8e9f632da1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2305,7 +2305,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 * Explicitly stating here that this seems to be currently
 	 * rather a Hack, than final solution.
 	 */
-	if (IS_TIGERLAKE(dev_priv)) {
+	if (IS_TIGERLAKE(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
 		/*
 		 * Clamp to max_cdclk_freq in case pixel rate is higher,
 		 * in order not to break an 8K, but still leave W/A at place.
-- 
2.24.1.485.gad05a3d8e5