[PATCH 04/16] Revert "drm/i915/display: Wait PSR2 get out of deep sleep to update pipe"
José Roberto de Souza
jose.souza at intel.com
Tue Sep 28 23:52:47 UTC 2021
This reverts commit b880e48b5791424c68a76bb0c92cc5299f94d0a6.
---
.../drm/i915/display/intel_display_debugfs.c | 3 +-
drivers/gpu/drm/i915/display/intel_psr.c | 64 +++++++------------
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_uncore.c | 47 --------------
drivers/gpu/drm/i915/intel_uncore.h | 7 --
5 files changed, 26 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 662596adb1da6..68f4ba8c46e75 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -303,7 +303,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
};
val = intel_de_read(dev_priv,
EDP_PSR2_STATUS(intel_dp->psr.transcoder));
- status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
+ status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
+ EDP_PSR2_STATUS_STATE_SHIFT;
if (status_val < ARRAY_SIZE(live_status))
status = live_status[status_val];
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a1ad0db1693e6..89ff3649ace15 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1792,33 +1792,15 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state)
_intel_psr_post_plane_update(state, crtc_state);
}
-static bool _is_psr2_read_for_pipe_update(void *data)
-{
- struct intel_dp *intel_dp = data;
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 val;
-
- val = intel_uncore_read_fw(&dev_priv->uncore,
- EDP_PSR2_STATUS(intel_dp->psr.transcoder));
- val &= EDP_PSR2_STATUS_STATE_MASK;
-
- return val == EDP_PSR2_STATUS_STATE_SLEEP || val == EDP_PSR2_STATUS_STATE_IDLE;
-}
-
-static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- unsigned int fw;
-
- fw = intel_uncore_forcewake_for_reg(&dev_priv->uncore,
- EDP_PSR2_STATUS(intel_dp->psr.transcoder),
- FW_REG_READ);
- return intel_wait_for_condition(&dev_priv->uncore,
- _is_psr2_read_for_pipe_update,
- intel_dp, fw, 50);
-}
-
-static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
+/**
+ * psr_wait_for_idle - wait for PSR1 to idle
+ * @intel_dp: Intel DP
+ * @out_value: PSR status in case of failure
+ *
+ * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
+ *
+ */
+static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1828,13 +1810,15 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
- return intel_de_wait_for_clear(dev_priv,
- EDP_PSR_STATUS(intel_dp->psr.transcoder),
- EDP_PSR_STATUS_STATE_MASK, 50);
+ return __intel_wait_for_register(&dev_priv->uncore,
+ EDP_PSR_STATUS(intel_dp->psr.transcoder),
+ EDP_PSR_STATUS_STATE_MASK,
+ EDP_PSR_STATUS_STATE_IDLE, 2, 50,
+ out_value);
}
/**
- * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
+ * intel_psr_wait_for_idle - wait for PSR1 to idle
* @new_crtc_state: new CRTC state
*
* This function is expected to be called from pipe_update_start() where it is
@@ -1851,23 +1835,19 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- int ret;
+ u32 psr_status;
mutex_lock(&intel_dp->psr.lock);
-
- if (!intel_dp->psr.enabled) {
+ if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
mutex_unlock(&intel_dp->psr.lock);
continue;
}
- if (intel_dp->psr.psr2_enabled)
- ret = _psr2_ready_for_pipe_update_locked(intel_dp);
- else
- ret = _psr1_ready_for_pipe_update_locked(intel_dp);
-
- if (ret)
- drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
-
+ /* when the PSR1 is enabled */
+ if (psr_wait_for_idle(intel_dp, &psr_status))
+ drm_err(&dev_priv->drm,
+ "PSR idle timed out 0x%x, atomic update may fail\n",
+ psr_status);
mutex_unlock(&intel_dp->psr.lock);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ce1977aaacd3..ef594df039db7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4702,9 +4702,8 @@ enum {
#define _PSR2_STATUS_A 0x60940
#define _PSR2_STATUS_EDP 0x6f940
#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
-#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
-#define EDP_PSR2_STATUS_STATE_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x3)
-#define EDP_PSR2_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x0)
+#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
+#define EDP_PSR2_STATUS_STATE_SHIFT 28
#define _PSR2_SU_STATUS_A 0x60914
#define _PSR2_SU_STATUS_EDP 0x6f914
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1b3ea7318c2d5..678a99de07fee 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2383,28 +2383,6 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
#undef done
}
-static int __intel_wait_for_condition_fw(bool (*func)(void *data), void *data,
- unsigned int fast_timeout_us,
- unsigned int slow_timeout_ms)
-{
-#define done (func(data))
- int ret;
-
- /* Catch any overuse of this function */
- might_sleep_if(slow_timeout_ms);
- GEM_BUG_ON(fast_timeout_us > 20000);
- GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
-
- ret = -ETIMEDOUT;
- if (fast_timeout_us && fast_timeout_us <= 20000)
- ret = _wait_for_atomic(done, fast_timeout_us, 0);
- if (ret && slow_timeout_ms)
- ret = wait_for(done, slow_timeout_ms);
-
- return ret;
-#undef done
-}
-
/**
* __intel_wait_for_register - wait until register matches expected state
* @uncore: the struct intel_uncore
@@ -2464,31 +2442,6 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
return ret;
}
-int intel_wait_for_condition(struct intel_uncore *uncore,
- bool (*func)(void *data),
- void *data,
- unsigned int fw,
- unsigned int slow_timeout_ms)
-{
- unsigned int fast_timeout_us = 2;
- int ret;
-
- might_sleep_if(slow_timeout_ms);
-
- spin_lock_irq(&uncore->lock);
- intel_uncore_forcewake_get__locked(uncore, fw);
-
- ret = __intel_wait_for_condition_fw(func, data, fast_timeout_us, 0);
-
- intel_uncore_forcewake_put__locked(uncore, fw);
- spin_unlock_irq(&uncore->lock);
-
- if (ret && slow_timeout_ms)
- ret = __wait_for(, (func(data)), slow_timeout_ms * 1000, 10, 1000);
-
- return ret;
-}
-
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
{
bool ret;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index d6455824cbc56..2f31c50eeae24 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -282,7 +282,6 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
unsigned int fast_timeout_us,
unsigned int slow_timeout_ms,
u32 *out_value);
-
static inline int
intel_wait_for_register_fw(struct intel_uncore *uncore,
i915_reg_t reg,
@@ -294,12 +293,6 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
}
-int intel_wait_for_condition(struct intel_uncore *uncore,
- bool (*func)(void *data),
- void *data,
- unsigned int fw,
- unsigned int timeout_ms);
-
/* register access functions */
#define __raw_read(x__, s__) \
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
--
2.33.0
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