[PATCH 16/16] temp

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index de72a81f35ae8..c08faf8ef6e8b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1839,7 +1839,7 @@ static bool _is_psr2_read_for_pipe_update(void *data)
 				   EDP_PSR2_STATUS(intel_dp->psr.transcoder));
 	val &= EDP_PSR2_STATUS_STATE_MASK;
 
-	return val == EDP_PSR2_STATUS_STATE_SLEEP || val == EDP_PSR2_STATUS_STATE_IDLE;
+	return val != EDP_PSR2_STATUS_STATE_DEEP_SLEEP;
 }
 
 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ce1977aaacd3..4b71cdd4305e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4705,6 +4705,7 @@ enum {
 #define EDP_PSR2_STATUS_STATE_MASK     REG_GENMASK(31, 28)
 #define EDP_PSR2_STATUS_STATE_SLEEP    REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x3)
 #define EDP_PSR2_STATUS_STATE_IDLE     REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x0)
+#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP   REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
 
 #define _PSR2_SU_STATUS_A		0x60914
 #define _PSR2_SU_STATUS_EDP		0x6f914
-- 
2.33.0