[PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines

[Zbigniew Kempczyński]

Test verifies eviction works when all engines try to use same offset
for different handles.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
---
 tests/i915/gem_softpin.c | 90 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index 34fc9983ff..5b0f624414 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -898,6 +898,93 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j)
 	batches[j] = tmp;
 }
 
+static void single_offset_submit(int fd, int gen,
+				 struct drm_i915_gem_execbuffer2 *eb,
+				 struct batch *batches, unsigned int count)
+{
+	struct drm_i915_gem_exec_object2 obj;
+	uint64_t address = max_t(uint64_t, gem_detect_safe_start_offset(fd), 0x200000);
+
+	memset(&obj, 0, sizeof(obj));
+	obj.flags = EXEC_OBJECT_PINNED;
+
+	for (unsigned i = 0; i < count; i++) {
+		obj.handle = batches[i].handle;
+		obj.offset = address;
+		eb->buffers_ptr = to_user_pointer(&obj);
+		gem_execbuf(fd, eb);
+	}
+}
+
+static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
+{
+	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct intel_execution_engine2 *e;
+	unsigned engines[I915_EXEC_RING_MASK + 1];
+	struct batch *batches;
+	unsigned nengine;
+	unsigned count;
+	uint64_t size;
+
+	nengine = 0;
+	for_each_ctx_engine(fd, ctx, e) {
+		engines[nengine++] = e->flags;
+	}
+	igt_require(nengine);
+
+	size = gem_aperture_size(fd);
+	if (!gem_uses_full_ppgtt(fd))
+		size /= 2;
+	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
+		size = 1ull << 32;
+	igt_require(size < (1ull<<32) * BATCH_SIZE);
+
+	count = size / BATCH_SIZE + 1;
+	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
+		  count, (long long)size, nengine);
+
+	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
+	intel_detect_and_clear_missed_interrupts(fd);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffer_count = 1;
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+	execbuf.rsvd1 = ctx->id;
+
+	batches = calloc(count, sizeof(*batches));
+	igt_assert(batches);
+	for (unsigned i = 0; i < count; i++) {
+		uint32_t *p;
+
+		batches[i].handle = gem_create(fd, BATCH_SIZE);
+		batches[i].ptr =
+			gem_mmap__device_coherent(fd, batches[i].handle,
+						  0, BATCH_SIZE, PROT_WRITE);
+		p = batches[i].ptr + BATCH_SIZE - 8;
+		*p = MI_BATCH_BUFFER_END;
+	}
+
+	/* Flush all memory before we start the timer */
+	single_offset_submit(fd, gen, &execbuf, batches, count);
+
+	igt_fork(child, nengine) {
+		execbuf.flags |= engines[child];
+		igt_until_timeout(timeout)
+			single_offset_submit(fd, gen, &execbuf, batches, count);
+	}
+	igt_waitchildren();
+
+	for (unsigned i = 0; i < count; i++) {
+		munmap(batches[i].ptr, BATCH_SIZE);
+		gem_close(fd, batches[i].handle);
+	}
+	free(batches);
+
+	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+}
+
 static void submit(int fd, int gen,
 		   struct drm_i915_gem_execbuffer2 *eb,
 		   struct batch *batches, unsigned int count,
@@ -1209,6 +1296,9 @@ igt_main
 		igt_subtest("allocator-fork")
 			test_allocator_fork(fd);
 
+		igt_subtest("evict-single-offset")
+			evict_single_offset(fd, ctx, 20);
+
 		test_each_engine("allocator-evict", fd, ctx, e)
 			test_allocator_evict(fd, ctx, e->flags, 20);
 
-- 
2.32.0