[PATCH] drm/dp: Don't rewrite link config when setting phy CTS test pattern with LTTPR

[Khaled Almahallawy]

The sequence for Source DP PHY CTS automation[1]:
1- Emulate successful Link Training
2- Short HPD and Change link rates and number of lanes
3- Short HPD and Change PHY test pattern and swing/pre-emp levels

With DP PHY CTS setup as follow:

     [DPTX + on board LTTPR]------Main Link--->[Scope]
     	     	        ^                         |
			|                         |
			|                         |
			----------Aux Ch------>[Aux Emulator]

Writing to LINK_BW_SET on a port that has LTTPR is an indication for the
start of LT for LTTPR [Check DP 2.0 E11 - Sec 3.6.8.2 & 3.6.8.6.3]. As
LTTPR snoops LINL_BW_SET/LANE_COUNT_SET, it will stop sending DP signals
to DP Scope causing the measurements to fail.

This can be tested with monitor connected to LTTPR port by writing to
LINK_BW_SET as follow:

  igt/tools/dpcd_reg write --offset=0x100 --value 0x14 --device=2

OR

  printf '\x14' | sudo dd of=/dev/drm_dp_aux2 bs=1 count=1 conv=notrunc
  seek=$((0x100))

This single aux write causes the screen to blank, sending short HPD to
DPTX, setting LINK_STATUS_UPDATE = 1 in DPCD 0x204, and triggering LT.

However, sending the same aux write on a port without LTTPR, directly
to the monitor, has no effect.

Similar to the case without LTTPR, AUX emulator(DPR-100), which is used to
trigger PHY automation, writes to LINK_BW_SET/LANE_COUNT_SET has no effect,
but the LTTPR will stop sending DP signals anyway waiting for LT to happen.

The fix for this, is to not rewrite link config that is already done in
step 2 by modeset, and just change PHY test patterns and swing/pre-emph
levels.

[1]: LTTPR Re-timer PHY test procedure proposal
     https://groups.vesa.org/wg/Link/document/16521

Cc: Imre Deak <imre.deak at intel.com>
Cc: Jani Nikula <jani.nikula at intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
---
 drivers/gpu/drm/dp/drm_dp.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 580016a1b9eb..f72d48e59b89 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2613,17 +2613,8 @@ int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
 				struct drm_dp_phy_test_params *data, u8 dp_rev)
 {
 	int err, i;
-	u8 link_config[2];
 	u8 test_pattern;
 
-	link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
-	link_config[1] = data->num_lanes;
-	if (data->enhanced_frame_cap)
-		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
-	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
-	if (err < 0)
-		return err;
-
 	test_pattern = data->phy_pattern;
 	if (dp_rev < 0x12) {
 		test_pattern = (test_pattern << 2) &
-- 
2.25.1