[PATCH 5/9] drm/i915/display: Replace crtc_state's has_drrs by drrs_downclock_mode

[José Roberto de Souza]

Will be adding some additional control options to DRRS that will
require to have the DRRS downclock mode stored in the crtc_state.

So to optimize memory usage a bit here using it to replace has_drrs
as we can check if the drrs_downclock_mode pointer is different than
null to have the same behavior has has_drrs.

Cc: Vidya Srinivas <vidya.srinivas at intel.com>
Cc: Sean Paul <seanpaul at chromium.org>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c         | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_types.h   | 4 +++-
 drivers/gpu/drm/i915/display/intel_dp.c              | 2 +-
 drivers/gpu/drm/i915/display/intel_drrs.c            | 6 +++---
 5 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 17d0cad9e1686..efa7723d7de38 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5363,7 +5363,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 
 	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
 		    pipe_config->ips_enabled, pipe_config->double_wide,
-		    pipe_config->has_drrs);
+		    CRTC_STATE_HAS_DRRS(pipe_config));
 
 	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
 
@@ -7089,7 +7089,7 @@ static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_stat
 
 	if (!intel_drrs_crtc_copy_fastset(old_crtc_state, new_crtc_state)) {
 		new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
-		new_crtc_state->has_drrs = old_crtc_state->has_drrs;
+		new_crtc_state->drrs_downclock_mode = old_crtc_state->drrs_downclock_mode;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 799b0d2bbba18..735bdac258db3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1088,7 +1088,7 @@ static int intel_drrs_status(struct seq_file *m, struct drm_connector *connector
 
 		/* DRRS Supported */
 		seq_printf(m, "Enabled: %s\n",
-			   str_yes_no(crtc_state->has_drrs));
+			   str_yes_no(CRTC_STATE_HAS_DRRS(crtc_state)));
 
 		seq_printf(m, "Active: %s\n",
 			   str_yes_no(intel_drrs_is_active(crtc)));
@@ -1800,7 +1800,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
 		crtc_state = to_intel_crtc_state(crtc->base.state);
 
 		if (!crtc_state->hw.active ||
-		    !crtc_state->has_drrs)
+		    !CRTC_STATE_HAS_DRRS(crtc_state))
 			goto out;
 
 		commit = crtc_state->uapi.commit;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 408152f9f46a4..c809160fcf33b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1056,7 +1056,7 @@ struct intel_crtc_state {
 
 	/* m2_n2 for eDP downclock */
 	struct intel_link_m_n dp_m2_n2;
-	bool has_drrs;
+	const struct drm_display_mode *drrs_downclock_mode;
 
 	/* PSR is supported but might not be enabled due the lack of enabled planes */
 	bool has_psr;
@@ -1264,6 +1264,8 @@ enum drrs_refresh_rate {
 	DRRS_REFRESH_RATE_LOW,
 };
 
+#define CRTC_STATE_HAS_DRRS(crtc_state) (!!((crtc_state)->drrs_downclock_mode))
+
 #define INTEL_PIPE_CRC_ENTRIES_NR	128
 struct intel_pipe_crc {
 	spinlock_t lock;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e4a79c11fd255..97931f9e003ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1882,7 +1882,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
 		pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
 
-	pipe_config->has_drrs = true;
+	pipe_config->drrs_downclock_mode = downclock_mode;
 
 	pixel_clock = downclock_mode->clock;
 	if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 258ec8f5669dc..d04cb61e6f074 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -144,7 +144,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-	if (!crtc_state->has_drrs)
+	if (!CRTC_STATE_HAS_DRRS(crtc_state))
 		return;
 
 	if (!crtc_state->hw.active)
@@ -176,7 +176,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 
-	if (!old_crtc_state->has_drrs)
+	if (!CRTC_STATE_HAS_DRRS(old_crtc_state))
 		return;
 
 	if (!old_crtc_state->hw.active)
@@ -318,7 +318,7 @@ bool intel_drrs_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
 {
 	struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
 
-	if (!new_crtc_state->has_drrs)
+	if (!CRTC_STATE_HAS_DRRS(new_crtc_state))
 		return false;
 
 	/* m2_n2 register needs to already be set */
-- 
2.36.0