[PATCH 05/11] Revert "wip"
José Roberto de Souza
jose.souza at intel.com
Wed Apr 27 21:40:29 UTC 2022
This reverts commit ed50f667176515cddc20256e1bbec7303de7f1a7.
---
drivers/gpu/drm/drm_atomic_helper.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 20 ----
drivers/gpu/drm/i915/display/intel_display.c | 91 +------------------
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_dp.c | 40 ++------
drivers/gpu/drm/i915/display/intel_drrs.c | 11 +--
drivers/gpu/drm/i915/display/intel_psr.c | 2 -
8 files changed, 19 insertions(+), 155 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index f41e56132b155..9603193d2fa13 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -630,7 +630,6 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
if (!drm_mode_equal(&old_crtc_state->mode, &new_crtc_state->mode)) {
drm_dbg_atomic(dev, "[CRTC:%d:%s] mode changed\n",
crtc->base.id, crtc->name);
- drm_info(dev, "new mode=%s | zeh\n", new_crtc_state->mode.name);
new_crtc_state->mode_changed = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fc37dfd66441f..9e6fa59eabba7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2999,32 +2999,17 @@ static void intel_disable_ddi(struct intel_atomic_state *state,
old_conn_state);
}
-static void print_link_m_n(struct drm_device *dev, const struct intel_link_m_n *a)
-{
- drm_info(dev, "\t\tdata_m=%u | zeh\n", a->data_m);
- drm_info(dev, "\t\tdata_n=%u | zeh\n", a->data_n);
- drm_info(dev, "\t\tlink_m=%u | zeh\n", a->link_m);
- drm_info(dev, "\t\tlink_n=%u | zeh\n", a->link_n);
- drm_info(dev, "\t\ttu=%u | zeh\n", a->tu);
-}
-
static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
intel_backlight_update(state, encoder, crtc_state, conn_state);
drm_connector_update_privacy_screen(conn_state);
-
- drm_info(conn_state->connector->dev, "intel_ddi_update_pipe_dp called | zeh\n");
- print_link_m_n(conn_state->connector->dev, &crtc_state->dp_m_n);
- intel_cpu_transcoder_set_m1_n1(intel_crtc, crtc_state->cpu_transcoder, &crtc_state->dp_m_n);
}
void intel_ddi_update_pipe(struct intel_atomic_state *state,
@@ -3436,7 +3421,6 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
- struct intel_crtc *intel_crtc;
/* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3500,10 +3484,6 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
intel_psr_get_config(encoder, pipe_config);
-
- intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
- pipe_config->seamless_mode_switch = intel_crtc->drrs.seamless_mode_switch;
- drm_info(&dev_priv->drm, "intel_ddi_get_config seamless_mode_switch=%i | zeh\n", intel_crtc->drrs.seamless_mode_switch);
}
void intel_ddi_get_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e2767341b2bd..17d0cad9e1686 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2622,20 +2622,6 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- drm_info(&dev_priv->drm, "intel_crtc_compute_pixel_rate seamless_mode_switch=%i | zeh\n", crtc_state->seamless_mode_switch);
-
- if (crtc_state->seamless_mode_switch) {
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- const struct intel_crtc_state *old_crtc_state;
-
- old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
- crtc_state->pixel_rate = ilk_pipe_pixel_rate(old_crtc_state);
- drm_info(&dev_priv->drm, "intel_crtc_compute_pixel_rate pipe%c keeping preivous pixel_rate=%i | zeh\n",
- pipe_name(crtc->pipe), old_crtc_state->pixel_rate);
- return;
- }
-
if (HAS_GMCH(dev_priv))
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
crtc_state->pixel_rate =
@@ -2691,9 +2677,6 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
struct drm_display_mode *mode = &crtc_state->hw.mode;
struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
- drm_info(crtc_state->uapi.crtc->dev, "intel_crtc_readout_derived_state pipe%c | zeh\n", pipe_name(intel_crtc->pipe));
/*
* Start with the adjusted_mode crtc timings, which
@@ -2728,11 +2711,8 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
static void intel_encoder_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
encoder->get_config(encoder, crtc_state);
- drm_info(crtc_state->uapi.crtc->dev, "intel_encoder_get_config pipe%c | zeh\n", pipe_name(intel_crtc->pipe));
intel_crtc_readout_derived_state(crtc_state);
}
@@ -4635,7 +4615,6 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
return NULL;
crtc = intel_crtc_for_pipe(dev_priv, pipe);
- drm_info(&dev_priv->drm, "intel_encoder_current_mode pipe%c | zeh\n", pipe_name(crtc->pipe));
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -5384,7 +5363,7 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
pipe_config->ips_enabled, pipe_config->double_wide,
- pipe_config->has_seamless_automatic_drrs);
+ pipe_config->has_drrs);
intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
@@ -6299,7 +6278,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
- // here
PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
PIPE_CONF_CHECK_X(gamma_mode);
@@ -6370,11 +6348,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- // here
- if (!pipe_config->seamless_mode_switch) {
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
- PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
- }
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -6651,7 +6626,6 @@ verify_crtc_state(struct intel_crtc *crtc,
struct drm_atomic_state *state = old_crtc_state->uapi.state;
struct intel_crtc *master_crtc;
- // clears state
__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
intel_crtc_free_hw_state(old_crtc_state);
intel_crtc_state_reset(old_crtc_state, crtc);
@@ -6659,20 +6633,9 @@ verify_crtc_state(struct intel_crtc *crtc,
drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
crtc->base.name);
- drm_info(&dev_priv->drm, "verify_crtc_state pipe%c | zeh\n", pipe_name(crtc->pipe));
-
- drm_info(&dev_priv->drm, "old_crtc_state->uapi.state->allow_modeset=%i | zeh\n", old_crtc_state->uapi.state->allow_modeset);
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "new_crtc_state->uapi.state->allow_modeset=%i | zeh\n", new_crtc_state->uapi.state->allow_modeset);
- else
- drm_info(&dev_priv->drm, "!new_crtc_state->uapi.state | zeh\n");
pipe_config->hw.enable = new_crtc_state->hw.enable;
- drm_info(&dev_priv->drm, "old_crtc_state->seamless_mode_switch=%i new_crtc_state->seamless_mode_switch=%i | zeh\n",
- old_crtc_state->seamless_mode_switch, new_crtc_state->seamless_mode_switch);
- old_crtc_state->seamless_mode_switch = new_crtc_state->seamless_mode_switch;
-
intel_crtc_get_pipe_config(pipe_config);
/* we keep both pipes enabled on 830 */
@@ -7126,9 +7089,7 @@ static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_stat
if (!intel_drrs_crtc_copy_fastset(old_crtc_state, new_crtc_state)) {
new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
- new_crtc_state->has_seamless_drrs = old_crtc_state->has_seamless_drrs;
- new_crtc_state->has_seamless_automatic_drrs = old_crtc_state->has_seamless_automatic_drrs;
- new_crtc_state->seamless_mode_switch = old_crtc_state->seamless_mode_switch;
+ new_crtc_state->has_drrs = old_crtc_state->has_drrs;
}
}
@@ -7767,19 +7728,10 @@ static int intel_atomic_check(struct drm_device *dev,
continue;
}
- if (!new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c !new_crtc_state->uapi.state zeh\n", pipe_name(crtc->pipe));
-
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 1 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
ret = intel_crtc_prepare_cleared_state(state, crtc);
if (ret)
goto fail;
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 2 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
if (!new_crtc_state->hw.enable)
continue;
@@ -7787,9 +7739,6 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 3 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
ret = intel_atomic_check_bigjoiner(state, crtc);
if (ret)
goto fail;
@@ -7800,20 +7749,11 @@ static int intel_atomic_check(struct drm_device *dev,
if (!intel_crtc_needs_modeset(new_crtc_state))
continue;
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 4 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
ret = intel_modeset_pipe_config_late(new_crtc_state);
if (ret)
goto fail;
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 5 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
-
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 6 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
}
/**
@@ -7871,11 +7811,6 @@ static int intel_atomic_check(struct drm_device *dev,
continue;
intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
-
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c 7 new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
- drm_info(dev, "zeh check 7 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
if (any_ms && !check_digital_port_conflicts(state)) {
@@ -7941,11 +7876,6 @@ static int intel_atomic_check(struct drm_device *dev,
intel_dump_pipe_config(new_crtc_state, state,
intel_crtc_needs_modeset(new_crtc_state) ?
"[modeset]" : "[fastset]");
-
- if (new_crtc_state->uapi.state)
- drm_info(&dev_priv->drm, "intel_atomic_check pipe%c last new_crtc_state->uapi.state->allow_modeset=%i\n", pipe_name(crtc->pipe), new_crtc_state->uapi.state->allow_modeset);
-
- drm_info(dev, "zeh check final pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
return 0;
@@ -8526,8 +8456,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
new_crtc_state->update_pipe) {
modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
}
-
- drm_info(dev, "zeh1 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
intel_commit_modeset_disables(state);
@@ -8559,8 +8487,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
new_crtc_state->uapi.event = NULL;
}
-
- drm_info(dev, "zeh2 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
intel_encoders_update_prepare(state);
@@ -8571,8 +8497,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
intel_crtc_enable_flip_done(state, crtc);
-
- drm_info(dev, "zeh3 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
@@ -8599,8 +8523,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (new_crtc_state->do_async_flip)
intel_crtc_disable_flip_done(state, crtc);
-
- drm_info(dev, "zeh4 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
/*
@@ -8624,17 +8546,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
intel_optimize_watermarks(state, crtc);
-
- drm_info(dev, "zeh5 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
}
intel_dbuf_post_plane_update(state);
intel_psr_post_plane_update(state);
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
- drm_info(dev, "zeh6 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
intel_post_plane_update(state, crtc);
- drm_info(dev, "zeh7 pipe%c seamless_mode_switch=%i | zeh\n", pipe_name(crtc->pipe), new_crtc_state->seamless_mode_switch);
modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
@@ -10184,7 +10102,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_crtc_free_hw_state(crtc_state);
intel_crtc_state_reset(crtc_state, crtc);
- drm_info(&dev_priv->drm, "intel_modeset_readout_hw_state pipe%c | zeh\n", pipe_name(crtc->pipe));
intel_crtc_get_pipe_config(crtc_state);
crtc_state->hw.enable = crtc_state->hw.active;
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3bfb8a7642e5c..799b0d2bbba18 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1088,7 +1088,7 @@ static int intel_drrs_status(struct seq_file *m, struct drm_connector *connector
/* DRRS Supported */
seq_printf(m, "Enabled: %s\n",
- str_yes_no(crtc_state->has_seamless_automatic_drrs));
+ str_yes_no(crtc_state->has_drrs));
seq_printf(m, "Active: %s\n",
str_yes_no(intel_drrs_is_active(crtc)));
@@ -1800,7 +1800,7 @@ static int i915_drrs_ctl_set(void *data, u64 val)
crtc_state = to_intel_crtc_state(crtc->base.state);
if (!crtc_state->hw.active ||
- !crtc_state->has_seamless_automatic_drrs)
+ !crtc_state->has_drrs)
goto out;
commit = crtc_state->uapi.commit;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5b1c73cb4c7c..408152f9f46a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1056,9 +1056,7 @@ struct intel_crtc_state {
/* m2_n2 for eDP downclock */
struct intel_link_m_n dp_m2_n2;
- bool has_seamless_drrs;
- bool has_seamless_automatic_drrs;
- bool seamless_mode_switch;
+ bool has_drrs;
/* PSR is supported but might not be enabled due the lack of enabled planes */
bool has_psr;
@@ -1316,7 +1314,6 @@ struct intel_crtc {
unsigned int busy_frontbuffer_bits;
enum transcoder cpu_transcoder;
struct intel_link_m_n m_n, m2_n2;
- bool seamless_mode_switch; /* Only to be used by state readout */
} drrs;
int scanline_offset;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a7ab62b6934d2..e4a79c11fd255 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1834,8 +1834,9 @@ static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
}
-static bool can_enable_seamless_drrs(struct intel_connector *connector,
- const struct intel_crtc_state *pipe_config)
+static bool can_enable_drrs(struct intel_connector *connector,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_display_mode *downclock_mode)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -1858,10 +1859,8 @@ static bool can_enable_seamless_drrs(struct intel_connector *connector,
if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
return false;
- if (intel_panel_drrs_type(connector) != DRRS_TYPE_SEAMLESS)
- return false;
-
- return true;
+ return downclock_mode &&
+ intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
}
static void
@@ -1873,31 +1872,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
const struct drm_display_mode *downclock_mode =
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
int pixel_clock;
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
- const struct intel_crtc_state *old_pipe_config;
- struct intel_atomic_state *state;
-
- drm_info(&i915->drm, "intel_dp_drrs_compute_config pipe%c | zeh\n", pipe_name(intel_crtc->pipe));
-
- if (!can_enable_seamless_drrs(connector, pipe_config)) {
- if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
- intel_zero_m_n(&pipe_config->dp_m2_n2);
- return;
- }
-
- pipe_config->has_seamless_drrs = true;
- drm_info(&i915->drm, "\thas_seamless_drrs | zeh\n");
-
- state = to_intel_atomic_state(pipe_config->uapi.state);
- old_pipe_config = intel_atomic_get_old_crtc_state(state, intel_crtc);
- if (old_pipe_config && !state->base.allow_modeset &&
- !drm_mode_equal(&old_pipe_config->hw.adjusted_mode, &pipe_config->hw.adjusted_mode)) {
- pipe_config->seamless_mode_switch = true;
- drm_info(&i915->drm, "\tseamless_mode_switch | zeh\n");
- }
- // todo also check if downclock_mode is preferred mode
- if (!downclock_mode) {
+ if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
intel_zero_m_n(&pipe_config->dp_m2_n2);
return;
@@ -1906,8 +1882,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
- pipe_config->has_seamless_automatic_drrs = true;
- drm_info(&i915->drm, "\thas_seamless_automatic_drrs | zeh\n");
+ pipe_config->has_drrs = true;
pixel_clock = downclock_mode->clock;
if (pipe_config->splitter.enable)
@@ -2064,7 +2039,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock /= n;
}
- drm_info(&dev_priv->drm, "intel_dp_compute_config new dp_m_n computed | zeh\n");
intel_link_compute_m_n(output_bpp,
pipe_config->lane_count,
adjusted_mode->crtc_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 4801fa0a8f81f..258ec8f5669dc 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -143,12 +143,8 @@ static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *c
void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-
- crtc->drrs.seamless_mode_switch = crtc_state->seamless_mode_switch;
- drm_info(&i915->drm, "intel_drrs_activate crtc->drrs.seamless_mode_switch=%i | zeh\n", crtc->drrs.seamless_mode_switch);
- if (!crtc_state->has_seamless_automatic_drrs)
+ if (!crtc_state->has_drrs)
return;
if (!crtc_state->hw.active)
@@ -180,7 +176,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
- if (!old_crtc_state->has_seamless_automatic_drrs)
+ if (!old_crtc_state->has_drrs)
return;
if (!old_crtc_state->hw.active)
@@ -322,6 +318,9 @@ bool intel_drrs_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
{
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
+ if (!new_crtc_state->has_drrs)
+ return false;
+
/* m2_n2 register needs to already be set */
if (intel_cpu_transcoder_has_m2_n2(i915, new_crtc_state->cpu_transcoder))
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f7fc2b64f244..06db407e2749f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1011,8 +1011,6 @@ void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp;
u32 val;
- drm_info(&dev_priv->drm, "intel_psr_get_config\n");
-
if (!dig_port)
return;
--
2.36.0
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