[PATCH 08/11] debug
José Roberto de Souza
jose.souza at intel.com
Wed Apr 27 21:40:32 UTC 2022
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++
drivers/gpu/drm/i915/display/intel_drrs.c | 20 ++++++++++++++++++
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c37501b2ab419..1b73104c37b6f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2622,6 +2622,8 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ drm_info(&dev_priv->drm, "intel_crtc_compute_pixel_rate() crtc_state->seamless_mode_switch=%i | zeh\n", crtc_state->seamless_mode_switch);
+
if (HAS_GMCH(dev_priv))
/* FIXME calculate proper pipe pixel rate for GMCH pfit */
crtc_state->pixel_rate =
@@ -2651,11 +2653,19 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
intel_fuzzy_clock_check(crtc_state->pixel_rate,
old_crtc_state->pixel_rate))
crtc_state->pixel_rate = old_crtc_state->pixel_rate;
+ else
+ drm_info(&dev_priv->drm, "\told pixel rate is < than required pixel rate\n");
+
+ drm_info(&dev_priv->drm, "\tpixel_rate=%i | zeh\n", crtc_state->pixel_rate);
}
}
static void intel_crtc_get_pixel_rate(struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
+ drm_info(&dev_priv->drm, "intel_crtc_get_pixel_rate() crtc_state->seamless_mode_switch=%i | zeh\n", crtc_state->seamless_mode_switch);
+
if (crtc_state->seamless_mode_switch) {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2663,6 +2673,18 @@ static void intel_crtc_get_pixel_rate(struct intel_crtc_state *crtc_state)
crtc_state->pixel_rate = crtc->drrs.seamless_mode_switch_pixel_rate;
mutex_unlock(&crtc->drrs.mutex);
+ drm_info(&dev_priv->drm, "\tpixel_rate=%i | zeh\n", crtc_state->pixel_rate);
+
+ /*struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state;
+
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ //crtc_state->pixel_rate = ilk_pipe_pixel_rate(old_crtc_state);
+ crtc_state->pixel_rate = old_crtc_state->pixel_rate;
+
+ drm_info(&dev_priv->drm, "\tpixel_rate=%i | zeh\n", crtc_state->pixel_rate);*/
+
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d7d045bdf77af..3ebd0e9b0259c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1904,11 +1904,15 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
int pixel_clock;
+ drm_info(&i915->drm, "intel_dp_drrs_compute_config | zeh\n");
+
if (!can_enable_drrs(connector, pipe_config))
goto not_supported;
if (can_seamless_switch_mode(pipe_config)) {
pipe_config->seamless_mode_switch = true;
+ drm_info(&i915->drm, "\tseamless_mode_switch=true | zeh\n");
+
return;
}
@@ -1919,6 +1923,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay;
pipe_config->has_drrs = true;
+ drm_info(&i915->drm, "\thas_drrs=true | zeh\n");
pixel_clock = downclock_mode->clock;
if (pipe_config->splitter.enable)
@@ -1997,6 +2002,15 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
return ret;
}
+static void print_link_m_n(struct drm_device *dev, const struct intel_link_m_n *a)
+{
+ drm_info(dev, "\t\tdata_m=%u | zeh\n", a->data_m);
+ drm_info(dev, "\t\tdata_n=%u | zeh\n", a->data_n);
+ drm_info(dev, "\t\tlink_m=%u | zeh\n", a->link_m);
+ drm_info(dev, "\t\tlink_n=%u | zeh\n", a->link_n);
+ drm_info(dev, "\t\ttu=%u | zeh\n", a->tu);
+}
+
int
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -2087,6 +2101,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->port_clock,
&pipe_config->dp_m_n,
constant_n, pipe_config->fec_enable);
+ drm_info(&dev_priv->drm, "intel_dp_compute_config\n");
+ print_link_m_n(&dev_priv->drm, &pipe_config->dp_m_n);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index c242d3bd3a27a..2501eff0118e5 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -143,12 +143,18 @@ static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *c
void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ drm_info(&i915->drm, "intel_drrs_activate pipe%c | zeh\n", pipe_name(crtc->pipe));
mutex_lock(&crtc->drrs.mutex);
crtc->drrs.seamless_mode_switch_pixel_rate = crtc_state->seamless_mode_switch ?
crtc_state->pixel_rate : 0;
+ if (crtc->drrs.seamless_mode_switch_pixel_rate)
+ drm_info(&i915->drm, "\tseamless_mode_switch=1 | zeh\n");
+
if (!crtc_state->has_drrs)
goto unlock;
@@ -163,6 +169,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;
crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
crtc->drrs.busy_frontbuffer_bits = 0;
+ drm_info(&i915->drm, "\thas_drrs=1 | zeh\n");
intel_drrs_schedule_work(crtc);
@@ -179,6 +186,19 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ drm_info(&i915->drm, "intel_drrs_deactivate pipe%c | zeh\n", pipe_name(crtc->pipe));
+
+ if (crtc->drrs.seamless_mode_switch_pixel_rate)
+ drm_info(&i915->drm, "\tcrtc->drrs.seamless_mode_switchh=1 | zeh\n");
+ else if (crtc->drrs.cpu_transcoder != INVALID_TRANSCODER)
+ drm_info(&i915->drm, "\tcrtc->drrs.cpu_transcoder=1 | zeh\n");
+
+ if (old_crtc_state->seamless_mode_switch)
+ drm_info(&i915->drm, "\told_crtc_state->seamless_mode_switch=1 | zeh\n");
+ else if (old_crtc_state->has_drrs)
+ drm_info(&i915->drm, "\told_crtc_state->has_drrs=1 | zeh\n");
if (!old_crtc_state->has_drrs)
return;
--
2.36.0
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