[PATCH] drm/i915/combo_phy: Add Workaround to avoid flicker with HBR3 eDP Panels

[Ankit Nautiyal]

Wa_22012718247 : When Display PHY is configured in continuous
DCC calibration mode, the DCC (duty cycle correction) for the clock
erroneously goes through a state where the DCC code is 0x00 when it is
supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
distortion in the clock, which leads to a bit error. The issue is known
to be causing flickering with eDP HBR3 panels.

The work around configures the DCC in one-time-update mode.
This mode updates the DCC code one time during training and then
it does not change.  This will prevent on-the-fly updates so that the
glitch does not occur.

v2: Added helper function for DCC_MODE (Imre).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c  | 17 +++++++++++++++--
 .../gpu/drm/i915/display/intel_combo_phy_regs.h |  1 +
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 64890f39c3cc..036c106d07b9 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -226,6 +226,17 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	return false;
 }
 
+static u32 tgl_dcc_calibration_mode(struct drm_i915_private *dev_priv)
+{
+	/* Wa_22012718247:tgl,adlp,adls */
+	if (IS_TIGERLAKE(dev_priv) ||
+	    IS_ALDERLAKE_P(dev_priv) ||
+	    IS_ALDERLAKE_S(dev_priv))
+		return DCC_MODE_SELECT_ONCE;
+
+	return DCC_MODE_SELECT_CONTINUOSLY;
+}
+
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 				       enum phy phy)
 {
@@ -244,7 +255,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
 				     DCC_MODE_SELECT_MASK,
-				     DCC_MODE_SELECT_CONTINUOSLY);
+				     tgl_dcc_calibration_mode(dev_priv));
 	}
 
 	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
@@ -366,8 +377,10 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
 
 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+
+			/* WA_14014367875 Set DCC calibration mode to Read once*/
 			val &= ~DCC_MODE_SELECT_MASK;
-			val |= DCC_MODE_SELECT_CONTINUOSLY;
+			val |= tgl_dcc_calibration_mode(dev_priv);
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
index 2ed65193ca19..cf46f13401d1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
@@ -92,6 +92,7 @@
 #define ICL_PORT_PCS_DW1_LN(ln, phy)		_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
 #define   DCC_MODE_SELECT_MASK			(0x3 << 20)
 #define   DCC_MODE_SELECT_CONTINUOSLY		(0x3 << 20)
+#define   DCC_MODE_SELECT_ONCE			(0x0 << 20)
 #define   COMMON_KEEPER_EN			(1 << 26)
 #define   LATENCY_OPTIM_MASK			(0x3 << 2)
 #define   LATENCY_OPTIM_VAL(x)			((x) << 2)
-- 
2.25.1