[PATCH 1/3] drm/i915/display: s/dev_priv/i915 in bxt_set_cdclk()

[Anusha Srivatsa]

bxt_set_cdclk() will have code churn in the upcoming patches.
This patch only does the renaming which can be avoided in the
future patches that do change the functionality.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 68 +++++++++++-----------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..92923485d65e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1689,7 +1689,7 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
 	return 0xffff;
 }
 
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+static void bxt_set_cdclk(struct drm_i915_private *i915,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
@@ -1701,8 +1701,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	int ret;
 
 	/* Inform power controller of upcoming frequency change. */
-	if (DISPLAY_VER(dev_priv) >= 11)
-		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+	if (DISPLAY_VER(i915) >= 11)
+		ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
 					SKL_CDCLK_PREPARE_FOR_CHANGE,
 					SKL_CDCLK_READY_FOR_CHANGE,
 					SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1711,70 +1711,70 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * BSpec requires us to wait up to 150usec, but that leads to
 		 * timeouts; the 2ms used here is based on experiment.
 		 */
-		ret = snb_pcode_write_timeout(&dev_priv->uncore,
+		ret = snb_pcode_write_timeout(&i915->uncore,
 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
 					      0x80000000, 150, 2);
 	if (ret) {
-		drm_err(&dev_priv->drm,
+		drm_err(&i915->drm,
 			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
 			ret, cdclk);
 		return;
 	}
 
-	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
-		if (dev_priv->cdclk.hw.vco != vco)
-			adlp_cdclk_pll_crawl(dev_priv, vco);
-	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		if (dev_priv->cdclk.hw.vco != 0 &&
-		    dev_priv->cdclk.hw.vco != vco)
-			icl_cdclk_pll_disable(dev_priv);
+	if (HAS_CDCLK_CRAWL(i915) && i915->cdclk.hw.vco > 0 && vco > 0) {
+		if (i915->cdclk.hw.vco != vco)
+			adlp_cdclk_pll_crawl(i915, vco);
+	} else if (DISPLAY_VER(i915) >= 11) {
+		if (i915->cdclk.hw.vco != 0 &&
+		    i915->cdclk.hw.vco != vco)
+			icl_cdclk_pll_disable(i915);
 
-		if (dev_priv->cdclk.hw.vco != vco)
-			icl_cdclk_pll_enable(dev_priv, vco);
+		if (i915->cdclk.hw.vco != vco)
+			icl_cdclk_pll_enable(i915, vco);
 	} else {
-		if (dev_priv->cdclk.hw.vco != 0 &&
-		    dev_priv->cdclk.hw.vco != vco)
-			bxt_de_pll_disable(dev_priv);
+		if (i915->cdclk.hw.vco != 0 &&
+		    i915->cdclk.hw.vco != vco)
+			bxt_de_pll_disable(i915);
 
-		if (dev_priv->cdclk.hw.vco != vco)
-			bxt_de_pll_enable(dev_priv, vco);
+		if (i915->cdclk.hw.vco != vco)
+			bxt_de_pll_enable(i915, vco);
 	}
 
-	waveform = cdclk_squash_waveform(dev_priv, cdclk);
+	waveform = cdclk_squash_waveform(i915, cdclk);
 
 	if (waveform)
 		clock = vco / 2;
 	else
 		clock = cdclk;
 
-	if (has_cdclk_squasher(dev_priv)) {
+	if (has_cdclk_squasher(i915)) {
 		u32 squash_ctl = 0;
 
 		if (waveform)
 			squash_ctl = CDCLK_SQUASH_ENABLE |
 				CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
 
-		intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+		intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
 	}
 
-	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
+	val = bxt_cdclk_cd2x_div_sel(i915, clock, vco) |
+		bxt_cdclk_cd2x_pipe(i915, pipe) |
 		skl_cdclk_decimal(cdclk);
 
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
 	 * enable otherwise.
 	 */
-	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
+	if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
 	    cdclk >= 500000)
 		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
-	intel_de_write(dev_priv, CDCLK_CTL, val);
+	intel_de_write(i915, CDCLK_CTL, val);
 
 	if (pipe != INVALID_PIPE)
-		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
+		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, pipe));
 
-	if (DISPLAY_VER(dev_priv) >= 11) {
-		ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
+	if (DISPLAY_VER(i915) >= 11) {
+		ret = snb_pcode_write(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
 				      cdclk_config->voltage_level);
 	} else {
 		/*
@@ -1783,27 +1783,27 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		 * FIXME: Waiting for the request completion could be delayed
 		 * until the next PCODE request based on BSpec.
 		 */
-		ret = snb_pcode_write_timeout(&dev_priv->uncore,
+		ret = snb_pcode_write_timeout(&i915->uncore,
 					      HSW_PCODE_DE_WRITE_FREQ_REQ,
 					      cdclk_config->voltage_level,
 					      150, 2);
 	}
 
 	if (ret) {
-		drm_err(&dev_priv->drm,
+		drm_err(&i915->drm,
 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
 			ret, cdclk);
 		return;
 	}
 
-	intel_update_cdclk(dev_priv);
+	intel_update_cdclk(i915);
 
-	if (DISPLAY_VER(dev_priv) >= 11)
+	if (DISPLAY_VER(i915) >= 11)
 		/*
 		 * Can't read out the voltage level :(
 		 * Let's just assume everything is as expected.
 		 */
-		dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+		i915->cdclk.hw.voltage_level = cdclk_config->voltage_level;
 }
 
 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
-- 
2.25.1