[PATCH 4/5] drm/i195/display: add cdclk action struct to cdclk_state

[Anusha Srivatsa]

The struct has the action to be performed - squash, crawl
or modeset and the corresponding cdclk which is the desired
cdclk. This is the structure that gets filled during
atomic check once it is determined what the cdclk change looks
like

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..34af6600e565 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -11,6 +11,8 @@
 #include "intel_display.h"
 #include "intel_global_state.h"
 
+#define	MAX_CDCLK_ACTIONS	1
+
 struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc_state;
@@ -20,6 +22,14 @@ struct intel_cdclk_config {
 	u8 voltage_level;
 };
 
+enum cdclk_sequence {
+	CDCLK_INVALID_ACTION = -1,
+
+	CDCLK_SQUASH_ONLY = 0,
+	CDCLK_CRAWL_ONLY,
+	CDCLK_LEGACY,
+};
+
 struct intel_cdclk_state {
 	struct intel_global_state base;
 
@@ -51,6 +61,11 @@ struct intel_cdclk_state {
 
 	/* bitmask of active pipes */
 	u8 active_pipes;
+
+	struct cdclk_step {
+		enum cdclk_sequence action;
+		u32 cdclk;
+	} steps[MAX_CDCLK_ACTIONS];
 };
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-- 
2.25.1