[PATCH] drm/i915: Ensure all plane register configured within one VBLANK

[Jouni Högander]

Writing any of the plane registers triggers frame change event to PSR
hw. The frame change event triggers update being sent to panel on next
frame. This is currently causing problems with continuous full frame
updates which are using SFF (Single Full Frame) bit. SFF bit is
cleared by the HW on VBLANK. Plane register writes are split into
_noarm and _arm and writing them may happen in two subsequent
VBLANKs. Both (_noarm and _arm) are triggering the frame change event to
PSR hw. If this happens the first update being sent after _noarm
doesn't have valid PSR2_TRK_MAN_CTL configuration as SFF bit is
cleared already by the HW in previous atomic commit.

Fix this by moving _noarm plane register writes to happen always in
same VBLANK as _arm plane registers and PSR2_TRK_MAN_CTL. This ensures
PSR HW sends only one update per atomic commit.

Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: José Roberto de Souza <jose.souza at intel.com>
Cc: Mika Kahola <mika.kahola at intel.com>

Reported-by: Lee Shawn C <shawn.c.lee at intel.com>
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 32b257157186..46e487ecc6ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7096,11 +7096,11 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	    intel_crtc_needs_color_update(new_crtc_state))
 		intel_color_commit_noarm(new_crtc_state);
 
-	intel_crtc_planes_update_noarm(state, crtc);
-
 	/* Perform vblank evasion around commit operation */
 	intel_pipe_update_start(new_crtc_state);
 
+	intel_crtc_planes_update_noarm(state, crtc);
+
 	commit_pipe_pre_planes(state, crtc);
 
 	intel_crtc_planes_update_arm(state, crtc);
-- 
2.34.1