[PATCH] drm/i915/gt: Use ggtt guard pages when dmar is enabled

[Thomas Hellström]

Test patch.

Signed-off-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 45 +++++++++++++---------------
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  2 ++
 2 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index bf94f8158c79..3b617a028b6d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -23,6 +23,16 @@
 #include "intel_gtt.h"
 #include "gen8_ppgtt.h"
 
+static void i915_ggtt_dmar_color_adjust(const struct drm_mm_node *node,
+					unsigned long color,
+					u64 *start,
+					u64 *end)
+{
+	if (*start)
+		*start += I915_GTT_PAGE_SIZE;
+	*end -= I915_GTT_PAGE_SIZE;
+}
+
 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
 				   unsigned long color,
 				   u64 *start,
@@ -53,8 +63,12 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
 	/* Only VLV supports read-only GGTT mappings */
 	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
 
-	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
+	if (!HAS_LLC(i915) && !HAS_PPGTT(i915)) {
+		GEM_BUG_ON(ggtt->has_guard_pages);
 		ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
+	} else if (ggtt->has_guard_pages) {
+		ggtt->vm.mm.color_adjust = i915_ggtt_dmar_color_adjust;
+	}
 
 	if (ggtt->mappable_end) {
 		if (!io_mapping_init_wc(&ggtt->iomap,
@@ -270,11 +284,15 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 {
 	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);
 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
+	unsigned long num_entries = vma_res->node_size / I915_GTT_PAGE_SIZE;
 	gen8_pte_t __iomem *gte;
 	gen8_pte_t __iomem *end;
 	struct sgt_iter iter;
 	dma_addr_t addr;
 
+	if (ggtt->has_guard_pages)
+		num_entries += 1;
+
 	/*
 	 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
 	 * not to allow the user to override access to a read only page.
@@ -282,7 +300,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 
 	gte = (gen8_pte_t __iomem *)ggtt->gsm;
 	gte += vma_res->start / I915_GTT_PAGE_SIZE;
-	end = gte + vma_res->node_size / I915_GTT_PAGE_SIZE;
+	end = gte + num_entries;
 
 	for_each_sgt_daddr(addr, iter, vma_res->bi.pages)
 		gen8_set_pte(gte++, pte_encode | addr);
@@ -355,27 +373,6 @@ static void nop_clear_range(struct i915_address_space *vm,
 {
 }
 
-static void gen8_ggtt_clear_range(struct i915_address_space *vm,
-				  u64 start, u64 length)
-{
-	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
-	unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
-	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
-	const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
-	gen8_pte_t __iomem *gtt_base =
-		(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
-	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
-	int i;
-
-	if (WARN(num_entries > max_entries,
-		 "First entry = %d; Num entries = %d (max=%d)\n",
-		 first_entry, num_entries, max_entries))
-		num_entries = max_entries;
-
-	for (i = 0; i < num_entries; i++)
-		gen8_set_pte(&gtt_base[i], scratch_pte);
-}
-
 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
 {
 	/*
@@ -974,7 +971,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	ggtt->vm.insert_page = gen8_ggtt_insert_page;
 	ggtt->vm.clear_range = nop_clear_range;
 	if (intel_scanout_needs_vtd_wa(i915))
-		ggtt->vm.clear_range = gen8_ggtt_clear_range;
+		ggtt->has_guard_pages = true;
 
 	ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index c3a8d6349f71..de57129f1d79 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -356,6 +356,8 @@ struct i915_ggtt {
 	struct mutex error_mutex;
 	struct drm_mm_node error_capture;
 	struct drm_mm_node uc_fw;
+
+	bool has_guard_pages : 1;
 };
 
 struct i915_ppgtt {
-- 
2.34.1