[PATCH 3/8] drm/i915: Initialize SCDC helper structures

Sun Mar 6 23:32:41 UTC 2022

> -----Original Message-----
> From: Intel-gfx-trybot <intel-gfx-trybot-bounces at lists.freedesktop.org> On Behalf
> Of Ankit Nautiyal
> Sent: Friday, March 4, 2022 12:22 PM
> To: intel-gfx-trybot at lists.freedesktop.org
> Subject: [PATCH 3/8] drm/i915: Initialize SCDC helper structures
> 
> This patch adds structures to get SCDC RR interrupt and initialize them.
> The callbacks for the work function and scdc irq setup are intentionally left and will
> be filled as we get other bits in place.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar at intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 21 ++++++++++++
> drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_irq.h |  2 ++
>  3 files changed, 81 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 79f0a40713f6..9772c26fcbf6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -104,6 +104,7 @@ struct intel_initial_plane_config;  struct intel_limit;  struct
> intel_overlay;  struct intel_overlay_error_state;
> +struct intel_scdc_funcs;
>  struct vlv_s0ix_state;
> 
>  /* Threshold == 5 for long IRQs, 50 for short */ @@ -163,6 +164,22 @@ enum
> scdc_pin {
>  	SCDC_NUM_PINS
>  };
> 
> +struct i915_scdc_read_request {
> +
> +	const u32 *scdc;
> +
> +	struct {
> +		enum {
> +			SCDC_ENABLED = 0,
> +			SCDC_DISABLED = 1,
> +		} state;
> +	} stats[SCDC_NUM_PINS];
> +	u32 event_bits;
> +
> +	struct work_struct scdc_rr_work;
> +	struct workqueue_struct *scdc_wq;
> +};
> +
>  #define I915_GEM_GPU_DOMAINS \
>  	(I915_GEM_DOMAIN_RENDER | \
>  	 I915_GEM_DOMAIN_SAMPLER | \
> @@ -568,6 +585,7 @@ struct drm_i915_private {
> 
>  	struct i915_hotplug hotplug;
>  	struct intel_fbc *fbc[I915_MAX_FBCS];
> +	struct i915_scdc_read_request scdc_rr;
>  	struct i915_drrs drrs;
>  	struct intel_opregion opregion;
>  	struct intel_vbt_data vbt;
> @@ -632,6 +650,9 @@ struct drm_i915_private {
>  	/* irq display functions */
>  	const struct intel_hotplug_funcs *hotplug_funcs;
> 
> +	/* scdc irq display functions */
> +	const struct intel_scdc_funcs *scdc_funcs;
> +
>  	/* fdi display functions */
>  	const struct intel_fdi_funcs *fdi_funcs;
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index
> 73cebc6aa650..4dc2542146cd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -183,6 +183,18 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>  	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),  };
> 
> +static const u32 scdc_sde_icp[SCDC_NUM_PINS] = {
> +	[SCDC_PORT_A] = SDE_DDI_SCDC_RR_ICP(SCDC_PORT_A),
> +	[SCDC_PORT_B] = SDE_DDI_SCDC_RR_ICP(SCDC_PORT_B),
> +	[SCDC_PORT_C] = SDE_DDI_SCDC_RR_ICP(SCDC_PORT_C),
> +	[SCDC_PORT_TC1] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC1),
> +	[SCDC_PORT_TC2] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC2),
> +	[SCDC_PORT_TC3] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC3),
> +	[SCDC_PORT_TC4] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC4),
> +	[SCDC_PORT_TC5] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC5),
> +	[SCDC_PORT_TC6] = SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC6),
> +};
> +
>  static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)  {
>  	struct i915_hotplug *hpd = &dev_priv->hotplug; @@ -225,6 +237,15 @@
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>  		MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
>  }
> 
> +static void scdc_rr_work_func(struct work_struct *work) {
> +	struct drm_i915_private *dev_priv =
> +		container_of(work, struct drm_i915_private, scdc_rr.scdc_rr_work);
> +	/* #TODO Support for SCDC for GLK,CNL */
> +	if (DISPLAY_VER(dev_priv) < 11)
> +		return;
> +}
> +
>  static void
>  intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)  { @@ -
> 3395,6 +3416,12 @@ static void icp_hpd_irq_setup(struct drm_i915_private
> *dev_priv)
>  	icp_tc_hpd_detection_setup(dev_priv);
>  }
> 
> +static void icp_scdc_irq_setup(struct drm_i915_private *dev_priv) {
> +	if (DISPLAY_VER(dev_priv) < 11)
> +		return;
> +}
> +
>  static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
>  				 enum hpd_pin pin)
>  {
> @@ -4374,6 +4401,35 @@ void intel_hpd_irq_setup(struct drm_i915_private *i915)
>  		i915->hotplug_funcs->hpd_irq_setup(i915);
>  }
> 
> +struct intel_scdc_funcs {
> +	void (*scdc_irq_setup) (struct drm_i915_private *dev_priv); };
> +
> +static const struct intel_scdc_funcs icp_scdc_funcs = {
> +	.scdc_irq_setup = icp_scdc_irq_setup,
> +};
> +
> +static void intel_scdc_irq_init(struct drm_i915_private *dev_priv) {
> +	/* #TODO Support for SCDC for GLK,CNL */
> +	if (DISPLAY_VER(dev_priv) < 11)
> +		return;
> +
> +	/* Initialize work function */
> +	INIT_WORK(&dev_priv->scdc_rr.scdc_rr_work, scdc_rr_work_func);
> +
> +	/* Initialize SCDC pins */
> +	dev_priv->scdc_rr.scdc = scdc_sde_icp;
> +
> +	dev_priv->scdc_funcs = &icp_scdc_funcs; }
> +
> +void intel_scdc_irq_setup(struct drm_i915_private *i915) {
> +	if (i915->display_irqs_enabled && i915->scdc_funcs)
> +		i915->scdc_funcs->scdc_irq_setup(i915);
> +}
> +
>  /**
>   * intel_irq_init - initializes irq support
>   * @dev_priv: i915 device instance
> @@ -4441,6 +4497,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		else
>  			dev_priv->hotplug_funcs = &ilk_hpd_funcs;
>  	}
> +
> +	intel_scdc_irq_init(dev_priv);
>  }
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index
> 82639d9d7e82..b5034259106f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -42,6 +42,8 @@ void i915_hotplug_interrupt_update(struct drm_i915_private
> *dev_priv,
>  				   u32 mask,
>  				   u32 bits);
> 
> +void intel_scdc_irq_setup(struct drm_i915_private *i915);
> +
>  void ilk_enable_display_irq(struct drm_i915_private *i915, u32 bits);  void
> ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits);
> 
> --
> 2.25.1