[PATCH 02/11] drm/i915: Add SCDC RR Interrupt Registers

[Ankit Nautiyal]

Add registers for detecting SCDC RR Interrupt

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 943267393ecb..0c1221475fe0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -147,6 +147,21 @@ struct i915_hotplug {
 	struct workqueue_struct *dp_wq;
 };
 
+enum scdc_pin {
+	SCDC_PORT_NONE,
+	SCDC_PORT_A,
+	SCDC_PORT_B,
+	SCDC_PORT_C,
+	SCDC_PORT_TC1,
+	SCDC_PORT_TC2,
+	SCDC_PORT_TC3,
+	SCDC_PORT_TC4,
+	SCDC_PORT_TC5,
+	SCDC_PORT_TC6,
+
+	SCDC_NUM_PINS
+};
+
 #define I915_GEM_GPU_DOMAINS \
 	(I915_GEM_DOMAIN_RENDER | \
 	 I915_GEM_DOMAIN_SAMPLER | \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 70484f6f2b8b..0888642e6952 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1473,6 +1473,7 @@
 #define   GMBUS_RATE_1MHZ	(3 << 8) /* reserved on Pineview */
 #define   GMBUS_HOLD_EXT	(1 << 7) /* 300ns hold time, rsvd on Pineview */
 #define   GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
+#define   GMBUS_PIN_PAIR_SELECT_MASK	0x1F
 
 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
 #define   GMBUS_SW_CLR_INT	(1 << 31)
@@ -6074,6 +6075,19 @@
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
+#define _SCDC_PIN_DDI(scdc_pin)	((scdc_pin) - SCDC_PORT_A)
+#define _SCDC_PIN_TC(scdc_pin)	((scdc_pin) - SCDC_PORT_TC1)
+#define SDE_DDI_SCDC_RR_ICP(scdc_pin)	REG_BIT(0 + _SCDC_PIN_DDI(scdc_pin))
+#define SDE_TC_SCDC_RR_ICP(scdc_pin)	REG_BIT(8 + _SCDC_PIN_TC(scdc_pin))
+#define SDE_DDI_SCDC_MASK_ICP		(SDE_DDI_SCDC_RR_ICP(SCDC_PORT_C) | \
+					 SDE_DDI_SCDC_RR_ICP(SCDC_PORT_B) | \
+					 SDE_DDI_SCDC_RR_ICP(SCDC_PORT_A))
+#define SDE_TC_SCDC_MASK_ICP		(SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC6) | \
+					 SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC5) | \
+					 SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC4) | \
+					 SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC3) | \
+					 SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC2) | \
+					 SDE_TC_SCDC_RR_ICP(SCDC_PORT_TC1))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
-- 
2.25.1