[PATCH 8/8] aaaa

[José Roberto de Souza]

---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f7b7b374374b1..08a3aaf1473c7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1195,6 +1195,7 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 		intel_dp->psr.sink_not_reliable = true;
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR interruption error set, not enabling PSR\n");
+		drm_err(&dev_priv->drm, "intel_psr_short_pulse 2\n");
 		return false;
 	}
 
@@ -2101,10 +2102,12 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
 
 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_psr *psr = &intel_dp->psr;
 
 	intel_psr_disable_locked(intel_dp);
 	psr->sink_not_reliable = true;
+	drm_err(&dev_priv->drm, "intel_psr_short_pulse 3\n");
 	/* let's make sure that sink is awaken */
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 }
@@ -2422,6 +2425,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp)
 	if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
 		intel_psr_disable_locked(intel_dp);
 		psr->sink_not_reliable = true;
+		drm_err(&dev_priv->drm, "intel_psr_short_pulse 4\n");
 		drm_dbg_kms(&dev_priv->drm,
 			    "ALPM lock timeout error, disabling PSR\n");
 
@@ -2445,6 +2449,7 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp)
 
 	if (val & DP_PSR_CAPS_CHANGE) {
 		intel_psr_disable_locked(intel_dp);
+		drm_err(&dev_priv->drm, "intel_psr_short_pulse 5\n");
 		psr->sink_not_reliable = true;
 		drm_dbg_kms(&dev_priv->drm,
 			    "Sink PSR capability changed, disabling PSR\n");
@@ -2480,6 +2485,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
 	if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
 		intel_psr_disable_locked(intel_dp);
 		psr->sink_not_reliable = true;
+		drm_err(&dev_priv->drm, "intel_psr_short_pulse 1\n");
 	}
 
 	if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
-- 
2.35.1