[PATCH 2/2] drm/display/i915: Pass cdclk_state as parameter to platform_set_cdclk from modeset functions

[Anusha Srivatsa]

Pass cdclk_state from modeset functions so
we can get reference to atomic_state and eventually
to new_cdclk_state through which we can access the new stesp struct.

With this we can hopefull modularize bxt_set_cdclk to have
the various checks moved to atomic check phase and only
check for the steps struct values to perform the
required set of actions - squash, crawl or modeset

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 40 +++++++++++++++-------
 1 file changed, 28 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed05070b7307..5bd00583d59d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -69,7 +69,7 @@
 struct intel_cdclk_funcs {
 	void (*get_cdclk)(struct drm_i915_private *i915,
 			  struct intel_cdclk_config *cdclk_config);
-	void (*set_cdclk)(struct drm_i915_private *i915,
+	void (*set_cdclk)(struct intel_cdclk_state *state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe);
 	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
@@ -83,10 +83,11 @@ void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
 }
 
 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+				  struct intel_cdclk_state *state,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
 {
-	dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
+	dev_priv->display.funcs.cdclk->set_cdclk(state, cdclk_config, pipe);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -576,10 +577,12 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 		    intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
 }
 
-static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
+static void vlv_set_cdclk(struct intel_cdclk_state *cdclk_state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
+	struct intel_atomic_state *state = cdclk_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int cdclk = cdclk_config->cdclk;
 	u32 val, cmd = cdclk_config->voltage_level;
 	intel_wakeref_t wakeref;
@@ -665,10 +668,12 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 }
 
-static void chv_set_cdclk(struct drm_i915_private *dev_priv,
+static void chv_set_cdclk(struct intel_cdclk_state *cdclk_state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
+	struct intel_atomic_state *state = cdclk_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int cdclk = cdclk_config->cdclk;
 	u32 val, cmd = cdclk_config->voltage_level;
 	intel_wakeref_t wakeref;
@@ -784,10 +789,12 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
 	}
 }
 
-static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
+static void bdw_set_cdclk(struct intel_cdclk_state *cdclk_state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
+	struct intel_atomic_state *state = cdclk_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int cdclk = cdclk_config->cdclk;
 	int ret;
 
@@ -1066,10 +1073,12 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void skl_set_cdclk(struct drm_i915_private *dev_priv,
+static void skl_set_cdclk(struct intel_cdclk_state *cdclk_state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
+	struct intel_atomic_state *state = cdclk_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int cdclk = cdclk_config->cdclk;
 	int vco = cdclk_config->vco;
 	u32 freq_select, cdclk_ctl;
@@ -1183,6 +1192,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config;
+	struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
 
 	skl_sanitize_cdclk(dev_priv);
 
@@ -1206,18 +1216,19 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+	skl_set_cdclk(cdclk_state, &cdclk_config, INVALID_PIPE);
 }
 
 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
+	struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
 
 	cdclk_config.cdclk = cdclk_config.bypass;
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+	skl_set_cdclk(cdclk_state, &cdclk_config, INVALID_PIPE);
 }
 
 static bool has_cdclk_squasher(struct drm_i915_private *i915)
@@ -1689,10 +1700,12 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
 	return 0xffff;
 }
 
-static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
+static void bxt_set_cdclk(struct intel_cdclk_state *cdclk_state,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
+	struct intel_atomic_state *state = cdclk_state->base.state;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	int cdclk = cdclk_config->cdclk;
 	int vco = cdclk_config->vco;
 	u32 val;
@@ -1877,6 +1890,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
 
 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
 {
+	struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
 	struct intel_cdclk_config cdclk_config;
 
 	bxt_sanitize_cdclk(dev_priv);
@@ -1897,19 +1911,20 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
 
-	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+	bxt_set_cdclk(cdclk_state, &cdclk_config, INVALID_PIPE);
 }
 
 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
+	struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
 
 	cdclk_config.cdclk = cdclk_config.bypass;
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
 
-	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
+	bxt_set_cdclk(cdclk_state, &cdclk_config, INVALID_PIPE);
 }
 
 /**
@@ -2076,6 +2091,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 			    enum pipe pipe)
 {
 	struct intel_encoder *encoder;
+	struct intel_cdclk_state *cdclk_state = to_intel_cdclk_state(dev_priv->display.cdclk.obj.state);
 
 	if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
 		return;
@@ -2106,7 +2122,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 				     &dev_priv->display.gmbus.mutex);
 	}
 
-	intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
+	intel_cdclk_set_cdclk(dev_priv, cdclk_state, cdclk_config, pipe);
 
 	for_each_intel_dp(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-- 
2.25.1