[PATCH] drm/i915/display: Fix PHY CTS DDI disable/enable sequence

[Khaled Almahallawy]

This patch address some issues observed with disable/enable code:

1- Based on Spec:50482, no need to disable/enable DP_TP_CTL before
enabling test pattern. When DP_TP_CTL is disabled, garbage signals
are observed. When these garbage signals are fed into LTTPR, and then
DP_TP_CTL is enabled, the PHY patterns out of LTTPR will be corrupted.
Seems LTTPR are not able to recover and produce clean PHY patterns
after that. Avoid all these by removing disable/enable code for DP_TP_CTL

2- Only set Bit:31 for TRANS_DDI_FUNC_CTL disabling.

3- While we are here, support Display_ver < 12 for enabling sequence.

Cc: Imre Deak <imre.deak at intel.com>
Cc: Clint Taylor <clinton.a.taylor at intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a5eca5396fed..584a7dbeb4a9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3695,22 +3695,18 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+	u32 trans_ddi_func_ctl_value, trans_conf_value;
 
 	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
 						 TRANS_DDI_FUNC_CTL(pipe));
 	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
 
-	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
-				      TGL_TRANS_DDI_PORT_MASK);
+	trans_ddi_func_ctl_value &= ~TRANS_DDI_FUNC_ENABLE;
 	trans_conf_value &= ~PIPECONF_ENABLE;
-	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
 
 	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
 	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
 		       trans_ddi_func_ctl_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
 }
 
 static void
@@ -3723,20 +3719,21 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
 	enum port port = dig_port->base.port;
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
+	u32 trans_ddi_func_ctl_value, trans_conf_value;
 
 	trans_ddi_func_ctl_value = intel_de_read(dev_priv,
 						 TRANS_DDI_FUNC_CTL(pipe));
 	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
-	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
 
-	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
-				    TGL_TRANS_DDI_SELECT_PORT(port);
+	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE;
+	if (DISPLAY_VER(dev_priv) >= 12)
+		trans_ddi_func_ctl_value |= TGL_TRANS_DDI_SELECT_PORT(port);
+	else
+		trans_ddi_func_ctl_value |= TRANS_DDI_SELECT_PORT(port);
+
 	trans_conf_value |= PIPECONF_ENABLE;
-	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
 
 	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
-	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
 	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
 		       trans_ddi_func_ctl_value);
 }
-- 
2.25.1