[PATCH 10/11] HAX: Debugging for lockdep splat

[Matt Roper]

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c      |  6 +++++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 ++++++++++++--
 drivers/gpu/drm/i915/i915_trace.h           | 27 +++++++++++++++++++++
 3 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e79405a45312..d25e37265f11 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -4,6 +4,7 @@
  */
 
 #include "i915_drv.h"
+#include "i915_trace.h"
 
 #include "intel_gt_mcr.h"
 #include "intel_gt_regs.h"
@@ -194,6 +195,11 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
 
 	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
 
+	if (rw_flag == FW_REG_WRITE)
+		trace_i915_mcr_rw(true, reg, value, group, instance);
+	else
+		trace_i915_mcr_rw(false, reg, val, group, instance);
+
 	return val;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 278b022bcea0..fd5b2dad88fa 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1672,6 +1672,9 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
 
 	fw = wal_get_fw_for_rmw(uncore, wal);
 
+	printk("MDR :: Applying workaround list %s %s\n",
+	       wal->name, wal->engine_name ?: "<none>");
+
 	spin_lock_irqsave(&uncore->lock, flags);
 	intel_uncore_forcewake_get__locked(uncore, fw);
 
@@ -1679,18 +1682,29 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
 		u32 val, old = 0;
 
 		/* open-coded rmw due to steering */
+		if (wa->clr)
+			printk("MDR ::  - Reading 0x%x\n", i915_mmio_reg_offset(wa->reg));
 		old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0;
 		val = (old & ~wa->clr) | wa->set;
-		if (val != old || !wa->clr)
+		if (val != old || !wa->clr) {
+			printk("MDR ::  - Writing 0x%x = 0x%x\n", i915_mmio_reg_offset(wa->reg), val);
 			intel_uncore_write_fw(uncore, wa->reg, val);
+		}
 
-		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
 			wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg),
 				  wal->name, "application");
+			printk("MDR ::  - Verifying 0x%x\n",
+			       i915_mmio_reg_offset(wa->reg));
+		}
 	}
 
 	intel_uncore_forcewake_put__locked(uncore, fw);
 	spin_unlock_irqrestore(&uncore->lock, flags);
+
+	printk("MDR :: Done applying workaround list %s %s\n",
+	       wal->name, wal->engine_name ?: "<none>");
+
 }
 
 void intel_gt_apply_workarounds(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 37b5c9e9d260..f12f4eefadb3 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -671,6 +671,33 @@ TRACE_EVENT_CONDITION(i915_reg_rw,
 		(u32)(__entry->val >> 32))
 );
 
+TRACE_EVENT(i915_mcr_rw,
+	TP_PROTO(bool write, i915_reg_t reg, u32 val,
+		 int group, int instance),
+	TP_ARGS(write, reg, val, group, instance),
+
+	TP_STRUCT__entry(
+		__field(u32, val)
+		__field(u32, reg)
+		__field(u16, write)
+		__field(u16, group)
+		__field(u16, instance)
+		),
+
+	TP_fast_assign(
+		__entry->val = val;
+		__entry->reg = i915_mmio_reg_offset(reg);
+		__entry->write = write;
+		__entry->group = group;
+		__entry->instance = instance;
+		),
+
+	TP_printk("%s MCR reg=0x%x[grp=%d inst=%d], val=0x%x",
+		  __entry->write ? "write" : "read",
+		  __entry->reg, __entry->group, __entry->instance,
+		  __entry->val)
+);
+
 TRACE_EVENT(intel_gpu_freq_change,
 	    TP_PROTO(u32 freq),
 	    TP_ARGS(freq),
-- 
2.37.3