[PATCH 1/4] drm/i915/display: Add cdclk_state in drm_i915_private

[Anusha Srivatsa]

All cdclk funcs have dev_priv in their siganture.
bxt_set_cdclk() needs to have access to the new_cdclk_state through
which the whole cdclk refactoring can happen. However right now
even though we are populating things in atomic check ohase properly,
the copy does not happen till much later  in atomic commit. By the
time bxt_set_cdclk is called we do not have access to the new values.

Hence, making a copy of the new_cdclk_state in intel_modeset_calc_cdclk
to see if we can access the new cdclk state values from bxt_set_cdclk()

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c        | 2 ++
 drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed05070b7307..b645ac57f4a9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2785,6 +2785,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 			    "Modeset required for cdclk change\n");
 	}
 
+	dev_priv->display.cdclk_state = new_cdclk_state;
+
 	drm_dbg_kms(&dev_priv->drm,
 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
 		    new_cdclk_state->logical.cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9086a612365e..58eca1374d50 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -306,6 +306,8 @@ struct intel_display {
 		unsigned int max_cdclk_freq;
 	} cdclk;
 
+	struct intel_cdclk_state *cdclk_state;
+
 	struct {
 		/* The current hardware dbuf configuration */
 		u8 enabled_slices;
-- 
2.25.1