[PATCH 05/10] drm/i915/xehp: Check for faults on all mslices

[Matt Roper]

The fault registers are multicast registers, replicated per-mslice
starting on Xe_HP.  When checking for faults, we should check each
mslice's instance of the register rather than just one of the instances.

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c      | 37 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  3 ++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index b59fb03ed274..7ac11d9ff3f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -296,6 +296,39 @@ static void gen6_check_faults(struct intel_gt *gt)
 	}
 }
 
+static void xehp_check_faults(struct intel_gt *gt)
+{
+	u32 fault;
+	int mslice;
+
+	/* Check each mslice's fault register */
+	for (mslice = 0; mslice < 4; mslice++) {
+		fault = intel_gt_mcr_read(gt, XEHP_RING_FAULT_REG, mslice, 0);
+		if (fault & RING_FAULT_VALID) {
+			u32 fault_data0, fault_data1;
+			u64 fault_addr;
+
+			fault_data0 = intel_gt_mcr_read(gt, XEHP_FAULT_TLB_DATA0, mslice, 0);
+			fault_data1 = intel_gt_mcr_read(gt, XEHP_FAULT_TLB_DATA1, mslice, 0);
+
+			fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+				     ((u64)fault_data0 << 12);
+
+			drm_dbg(&gt->i915->drm, "Unexpected fault\n"
+				"\tAddr: 0x%08x_%08x\n"
+				"\tAddress space: %s\n"
+				"\tEngine ID: %d\n"
+				"\tSource ID: %d\n"
+				"\tType: %d\n",
+				upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+				fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+				GEN8_RING_FAULT_ENGINE_ID(fault),
+				RING_FAULT_SRCID(fault),
+				RING_FAULT_FAULT_TYPE(fault));
+		}
+	}
+}
+
 static void gen8_check_faults(struct intel_gt *gt)
 {
 	struct intel_uncore *uncore = gt->uncore;
@@ -342,7 +375,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 	struct drm_i915_private *i915 = gt->i915;
 
 	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
-	if (GRAPHICS_VER(i915) >= 8)
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+		xehp_check_faults(gt);
+	else if (GRAPHICS_VER(i915) >= 8)
 		gen8_check_faults(gt);
 	else if (GRAPHICS_VER(i915) >= 6)
 		gen6_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 2b3539ed3393..f7d0c03eb0ac 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1019,11 +1019,14 @@
 #define GEN9_BLT_MOCS(i)			_MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
 
 #define GEN12_FAULT_TLB_DATA0			_MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0			_MMIO(0xceb8)
 #define GEN12_FAULT_TLB_DATA1			_MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1			_MMIO(0xcebc)
 #define   FAULT_VA_HIGH_BITS			(0xf << 0)
 #define   FAULT_GTT_SEL				(1 << 4)
 
 #define GEN12_RING_FAULT_REG			_MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG			_MMIO(0xcec4)
 #define   GEN8_RING_FAULT_ENGINE_ID(x)		(((x) >> 12) & 0x7)
 #define   RING_FAULT_GTTSEL_MASK		(1 << 11)
 #define   RING_FAULT_SRCID(x)			(((x) >> 3) & 0xff)
-- 
2.37.3