[PATCH 4/6] drm/i915/display: Plug crawl bits to atomic check

Anusha Srivatsa anusha.srivatsa at intel.com
Thu Sep 15 23:27:50 UTC 2022


Populate the new steps struct for crawl case.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a6e9de21b0c6..6fe2a711c407 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,7 +1705,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
 {
-	enum cdclk_sequence cdclk_transition = cdclk_config->steps->action;
 	int cdclk = cdclk_config->cdclk;
 	int vco = cdclk_config->vco;
 	u32 val;
@@ -1713,9 +1712,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	int clock;
 	int ret;
 
-	if (cdclk_transition == CDCLK_SQUASH_ONLY)
-		drm_err(&dev_priv->drm, "***Atomic has set Squash as the desired cdclk action\n");
-
 	/* Inform power controller of upcoming frequency change. */
 	if (DISPLAY_VER(dev_priv) >= 11)
 		ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
@@ -1955,8 +1951,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
 
 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
 				  const struct intel_cdclk_config *a,
-				  const struct intel_cdclk_config *b)
+				  struct intel_cdclk_config *b)
 {
+	struct cdclk_step *cdclk_transition = b->steps;
 	int a_div, b_div;
 
 	if (!HAS_CDCLK_CRAWL(dev_priv))
@@ -1969,6 +1966,12 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
 	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
 	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
 
+	if (a->vco != 0 && b->vco != 0 && a->vco != b->vco &&
+	    a_div == b_div && a->ref == b->ref) {
+		cdclk_transition->action = CDCLK_CRAWL_ONLY;
+                cdclk_transition->cdclk = b->cdclk;
+	}
+		
 	return a->vco != 0 && b->vco != 0 &&
 		a->vco != b->vco &&
 		a_div == b_div &&
-- 
2.25.1



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