[PATCH 6/6] drm/i915/display: Plug struct cdclk_step in bxt_set_cdclk()

[Anusha Srivatsa]

Use the populated value in the struct cdclk_step during atomic_check
and convert the multiple checks in bxt_set_cdclk() to a switch.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 59 +++++++++++++---------
 1 file changed, 34 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6a945fa22d67..63a3c08c16b5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1724,6 +1724,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	u16 waveform;
 	int clock;
 	int ret;
+	enum cdclk_sequence cdclk_sequence = cdclk_config->steps->action;
 
 	/* Inform power controller of upcoming frequency change. */
 	if (DISPLAY_VER(dev_priv) >= 11)
@@ -1746,34 +1747,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
-	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			adlp_cdclk_pll_crawl(dev_priv, vco);
-	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_disable(dev_priv);
-
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			icl_cdclk_pll_enable(dev_priv, vco);
-	} else {
-		if (dev_priv->display.cdclk.hw.vco != 0 &&
-		    dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_disable(dev_priv);
+	drm_dbg_kms(&dev_priv->drm, "CDCLK changing from %i to %i using %s\n",
+                    dev_priv->display.cdclk.hw.cdclk,
+                    cdclk, cdclk_sequence_to_string(cdclk_sequence));
 
-		if (dev_priv->display.cdclk.hw.vco != vco)
-			bxt_de_pll_enable(dev_priv, vco);
-	}
-
-	waveform = cdclk_squash_waveform(dev_priv, cdclk);
-
-	if (waveform)
-		clock = vco / 2;
-	else
-		clock = cdclk;
+	switch (cdclk_sequence) {
+	case CDCLK_SQUASH_ONLY:
+                waveform = cdclk_squash_waveform(dev_priv, cdclk);
+                dg2_prog_squash_ctl(dev_priv, waveform);
+                break;
+        case CDCLK_CRAWL_ONLY:
+                adlp_cdclk_pll_crawl(dev_priv, vco);
+                break;
+	case CDCLK_LEGACY:
+		if (DISPLAY_VER(dev_priv) >= 11) {
+			if (dev_priv->display.cdclk.hw.vco != 0 &&
+				dev_priv->display.cdclk.hw.vco != vco)
+				icl_cdclk_pll_disable(dev_priv);
+
+			if (dev_priv->display.cdclk.hw.vco != vco)
+				icl_cdclk_pll_enable(dev_priv, vco);
+		} else {
+			if (dev_priv->display.cdclk.hw.vco != 0 &&
+				dev_priv->display.cdclk.hw.vco != vco)
+				bxt_de_pll_disable(dev_priv);
+
+			if (dev_priv->display.cdclk.hw.vco != vco)
+				bxt_de_pll_enable(dev_priv, vco);
+		}
 
-	if (has_cdclk_squasher(dev_priv))
+		waveform = cdclk_squash_waveform(dev_priv, cdclk);
 		dg2_prog_squash_ctl(dev_priv, waveform);
+		break;
+	default:
+		drm_err(&dev_priv->drm, "Invalid CDCLK sequence requested");
+		return;
+	}
 
 	val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
 		bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1