[PATCH 1/2] drm/i915/dg2: Enable DMC error interrupts

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  3 +++
 drivers/gpu/drm/i915/i915_irq.c               | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               |  3 +++
 3 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 5e5e41644ddfd..3a740dbfdb297 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -53,6 +53,9 @@
 /* An event handler scheduled to run at a 1 kHz frequency. */
 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
 
+#define _DMC_STATUS			0x8F06C
+#define DMC_STATUS(i915, dmc_id)	_MMIO(_DMC_REG(i915, dmc_id, _DMC_STATUS))
+
 #define DMC_HTP_ADDR_SKL	0x00500034
 #define DMC_SSP_BASE		_MMIO(0x8F074)
 #define DMC_HTP_SKL		_MMIO(0x8F004)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 87cb05b3b6cea..1895f85d8761c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -38,6 +38,8 @@
 #include "display/intel_de.h"
 #include "display/intel_display_trace.h"
 #include "display/intel_display_types.h"
+#include "display/intel_dmc.h"
+#include "display/intel_dmc_regs.h"
 #include "display/intel_fifo_underrun.h"
 #include "display/intel_hotplug.h"
 #include "display/intel_lpe_audio.h"
@@ -2342,6 +2344,16 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		found = true;
 	}
 
+	if ((iir & (GEN8_DE_DMC_ERROR | GEN8_DE_DMC_EVENT))) {
+		if (printk_ratelimit())
+			drm_err(&dev_priv->drm,
+				"DMC interrupt (error:%s, event:%s, status:%08x)\n",
+				str_yes_no(iir & GEN8_DE_DMC_ERROR),
+				str_yes_no(iir & GEN8_DE_DMC_EVENT),
+				intel_de_read_fw(dev_priv, DMC_STATUS(dev_priv, DMC_FW_MAIN)));
+		found = true;
+	}
+
 	if (iir & GEN8_DE_EDP_PSR) {
 		struct intel_encoder *encoder;
 		u32 psr_iir;
@@ -2569,6 +2581,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				"Fault errors on pipe %c: 0x%08x\n",
 				pipe_name(pipe),
 				fault_errors);
+
+		if ((iir & GEN8_PIPEDMC_INTERRUPT) && printk_ratelimit())
+			drm_err(&dev_priv->drm,
+				"PIPEDMC interrupt on pipe %c (status:%08x)\n",
+				pipe_name(pipe),
+				intel_de_read_fw(dev_priv, DMC_STATUS(dev_priv, DMC_FW_PIPEA + pipe)));
 	}
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
@@ -3776,6 +3794,11 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
+	if (IS_DG2(dev_priv)) {
+		de_misc_masked |= GEN8_DE_DMC_EVENT | GEN8_DE_DMC_ERROR;
+		de_pipe_masked |= GEN8_PIPEDMC_INTERRUPT;
+	}
+
 	if (DISPLAY_VER(dev_priv) <= 10)
 		de_misc_masked |= GEN8_DE_MISC_GSE;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5003a5ffbc6a6..65a7827ad6a4d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5507,6 +5507,7 @@
 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
+#define  GEN8_PIPEDMC_INTERRUPT		(1 << 26)
 #define  XELPD_PIPE_SOFT_UNDERRUN	(1 << 22)
 #define  XELPD_PIPE_HARD_UNDERRUN	(1 << 21)
 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
@@ -5589,6 +5590,8 @@
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
 #define  GEN8_DE_MISC_GSE		(1 << 27)
+#define  GEN8_DE_DMC_ERROR		REG_BIT(25)
+#define  GEN8_DE_DMC_EVENT		REG_BIT(24)
 #define  GEN8_DE_EDP_PSR		(1 << 19)
 
 #define GEN8_PCU_ISR _MMIO(0x444e0)
-- 
2.37.1