[PATCH] drm/xe: sysfs entries to query vram fused min, max frequency

[Sujaritha Sundaresan]

Add sysfs entries to query fused min and max frequency of vram.

Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan at intel.com>
---
 drivers/gpu/drm/xe/xe_guc_pc.c    | 57 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_pcode.c     | 15 ++++++++
 drivers/gpu/drm/xe/xe_pcode.h     |  1 +
 drivers/gpu/drm/xe/xe_pcode_api.h | 16 +++++++++
 4 files changed, 89 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index c03bb58e7049..48db41a75082 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -20,6 +20,7 @@
 #include "xe_map.h"
 #include "xe_mmio.h"
 #include "xe_pcode.h"
+#include "xe_pcode_api.h"
 
 #define MCHBAR_MIRROR_BASE_SNB	0x140000
 
@@ -642,6 +643,56 @@ static const struct attribute *pc_attrs[] = {
 	NULL
 };
 
+static ssize_t freq_vram_rp0_show(struct device *dev, struct device_attribute *attr,
+                                      char *buff)
+{
+
+        struct xe_guc_pc *pc = dev_to_pc(dev);
+        struct xe_gt *gt = pc_to_gt(pc);
+        u32 val;
+        int err;
+
+        err = xe_pcode_read_p(gt, XEHP_PCODE_FREQUENCY_CONFIG,
+                            PCODE_MBOX_FC_SC_READ_FUSED_P0,
+                            PCODE_MBOX_DOMAIN_HBM, &val);
+        if (err)
+                return err;
+
+        /* data_out - Fused P0 for domain ID in units of 50 MHz */
+        val *= GT_FREQUENCY_MULTIPLIER;
+
+        return sysfs_emit(buff, "%u\n", val);
+}
+static DEVICE_ATTR_RO(freq_vram_rp0);
+
+static ssize_t freq_vram_rpn_show(struct device *dev, struct device_attribute *attr,
+                                      char *buff)
+{
+        struct xe_guc_pc *pc = dev_to_pc(dev);
+        struct xe_gt *gt = pc_to_gt(pc);
+        u32 val;
+        int err;
+
+        err = xe_pcode_read_p(gt, XEHP_PCODE_FREQUENCY_CONFIG,
+                            PCODE_MBOX_FC_SC_READ_FUSED_PN,
+                            PCODE_MBOX_DOMAIN_HBM, &val);
+        if (err)
+                return err;
+
+        /* data_out - Fused P0 for domain ID in units of 50 MHz */
+        val *= GT_FREQUENCY_MULTIPLIER;
+
+        return sysfs_emit(buff, "%u\n", val);
+}
+static DEVICE_ATTR_RO(freq_vram_rpn);
+
+static const struct attribute *vram_freq_attrs[] = {
+        &dev_attr_freq_vram_rp0.attr,
+        &dev_attr_freq_vram_rpn.attr,
+        NULL
+};
+
+
 static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
 {
 	struct xe_gt *gt = pc_to_gt(pc);
@@ -925,6 +976,12 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
 	if (err)
 		return err;
 
+	if(IS_DGFX(xe) && xe->info.platform != XE_DG2){
+		err = sysfs_create_files(gt->sysfs, vram_freq_attrs);
+		if (err)
+			return err;
+	}
+
 	err = drmm_add_action_or_reset(&xe->drm, pc_fini, pc);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 7f1bf2297f51..0ec9bd076cbc 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -104,6 +104,21 @@ int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1)
 	return err;
 }
 
+int xe_pcode_read_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val)
+{
+
+	u32 mbox;
+	int err;
+
+	mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, mbcmd)
+		| REG_FIELD_PREP(PCODE_MB_PARAM1, p1)
+		| REG_FIELD_PREP(PCODE_MB_PARAM2, p2);
+
+	err = xe_pcode_read(gt, mbox, val, NULL);
+
+	return err;
+}
+
 static int xe_pcode_try_request(struct xe_gt *gt, u32 mbox,
 				u32 request, u32 reply_mask, u32 reply,
 				u32 *status, bool atomic, int timeout_us)
diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
index 3b4aa8c1a3ba..143bb33b4dbb 100644
--- a/drivers/gpu/drm/xe/xe_pcode.h
+++ b/drivers/gpu/drm/xe/xe_pcode.h
@@ -14,6 +14,7 @@ int xe_pcode_init(struct xe_gt *gt);
 int xe_pcode_init_min_freq_table(struct xe_gt *gt, u32 min_gt_freq,
 				 u32 max_gt_freq);
 int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1);
+int xe_pcode_read_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val);
 int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
 			   int timeout_ms);
 #define xe_pcode_write(gt, mbox, val) \
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 837ff7c71280..93f07b2a2910 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -25,6 +25,22 @@
 #define PCODE_DATA0			XE_REG(0x138128)
 #define PCODE_DATA1			XE_REG(0x13812C)
 
+#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* xehp, pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE		0x0
+#define     PCODE_MBOX_DOMAIN_GT		0x1
+#define     PCODE_MBOX_DOMAIN_HBM		0x2
+#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
+#define     PCODE_MBOX_DOMAIN_MEDIA_SAMPLER	0x4
+#define     PCODE_MBOX_DOMAIN_SYSTOLIC_ARRAY	0x5
+#define     PCODE_MBOX_DOMAIN_CHIPLET		0x6
+#define     PCODE_MBOX_DOMAIN_BASE_CHIPLET_LINK	0x7
+#define     PCODE_MBOX_DOMAIN_BASE		0x8
+
 /* Min Freq QOS Table */
 #define   PCODE_WRITE_MIN_FREQ_TABLE	0x8
 #define   PCODE_READ_MIN_FREQ_TABLE	0x9
-- 
2.25.1