[PATCH] FIXME: drm/i915/cx0: Check and increase timeout threshold

[Mika Kahola]

From: Gustavo Sousa <gustavo.sousa at intel.com>

When a timeout happens in the bus, bump the threshold on the message bus
timer in an attempt to allow progress on the bus.

FIXME:
    Two comments here:

    1) Timeouts have been seen in one machine when reading SRAM
       registers. While this change "fixes" the timeout issues, further
       investigation is necessary to understand what is causing the
       timeout.

    2) Is this something we would want to keep in the code regardless of
       the outcome of (1)? Could it be useful for potential future
       timeout issues?

v2: Bump timeout directly to max value and rename function
    accordingly (Mika)

BSpec: 65156
Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c   | 18 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h  | 13 +++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dd489b50ad60..3569789fa54a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -29,6 +29,8 @@
 #define INTEL_CX0_LANE1		BIT(1)
 #define INTEL_CX0_BOTH_LANES	(INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
 
+#define INTEL_CX0_MSGBUS_TIMER_VAL_MAX	0x200
+
 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
 {
 	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
@@ -119,6 +121,18 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
 	intel_clear_response_ready_flag(i915, port, lane);
 }
 
+/*
+ * Check if there was a timeout detected by the hardware in the message bus
+ * and bump the threshold if so.
+ */
+static void intel_cx0_bus_bump_timer(struct drm_i915_private *i915,
+				     enum port port, int lane)
+{
+	intel_de_rmw(i915, XELPDP_PORT_MSGBUS_TIMER(port, lane),
+		     XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
+		     INTEL_CX0_MSGBUS_TIMER_VAL_MAX);
+}
+
 static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
 				  int command, int lane, u32 *val)
 {
@@ -191,6 +205,8 @@ static u8 __intel_cx0_read(struct drm_i915_private *i915, enum port port,
 
 	assert_dc_off(i915);
 
+	intel_cx0_bus_bump_timer(i915, port, lane);
+
 	/* 3 tries is assumed to be enough to read successfully */
 	for (i = 0; i < 3; i++) {
 		status = __intel_cx0_read_once(i915, port, lane, addr);
@@ -270,6 +286,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
 
 	assert_dc_off(i915);
 
+	intel_cx0_bus_bump_timer(i915, port, lane);
+
 	/* 3 tries is assumed to be enough to write successfully */
 	for (i = 0; i < 3; i++) {
 		status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index cb5d1be2ba19..e88743ca62e6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -110,6 +110,19 @@
 #define   CX0_P4PG_STATE_DISABLE			0xC
 #define   CX0_P2_STATE_RESET				0x2
 
+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_A			0x640d8
+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B			0x641d8
+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1		0x16f258
+#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2		0x16f458
+#define XELPDP_PORT_MSGBUS_TIMER(idx, lane)		_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
+										 _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
+										 _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
+										 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
+										 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
+#define   XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT		REG_BIT(31)
+#define   XELPDP_PORT_MSGBUS_TIMER_VAL_MASK		REG_GENMASK(23, 0)
+#define   XELPDP_PORT_MSGBUS_TIMER_VAL(val)		REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, val)
+
 #define _XELPDP_PORT_CLOCK_CTL_A			0x640E0
 #define _XELPDP_PORT_CLOCK_CTL_B			0x641E0
 #define _XELPDP_PORT_CLOCK_CTL_USBC1			0x16F260
-- 
2.34.1