[PATCH 10/10] HAX: Add verbose drm-info debugs in PXP
Alan Previn
alan.previn.teres.alexis at intel.com
Wed Jan 11 18:07:09 UTC 2023
HAX: Add verbose drm-info debugs in PXP
Signed-off-by: Alan Previn <alan.previn.teres.alexis at intel.com>
---
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 38 ++++++--
.../i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h | 6 ++
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 50 ++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c | 95 ++++++++++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 14 +++
7 files changed, 205 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
index 2d6c7faf1794..e1b2a6c7e079 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c
@@ -51,10 +51,8 @@ intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
}
}
-#define GSC_HECI_CMD_PKT_NONPRIV_SIZE 8
-
static void
-emit_gsc_heci_pkt_nonpriv(u32 *cs, struct intel_gsc_heci_non_priv_pkt *pkt)
+emit_gsc_heci_pkt_nonpriv(u32 *cs, struct intel_gsc_heci_non_priv_pkt *pkt, u64 batch_offset)
{
*cs++ = GSC_HECI_CMD_PKT;
*cs++ = lower_32_bits(pkt->addr_in);
@@ -64,9 +62,31 @@ emit_gsc_heci_pkt_nonpriv(u32 *cs, struct intel_gsc_heci_non_priv_pkt *pkt)
*cs++ = upper_32_bits(pkt->addr_out);
*cs++ = pkt->size_out;
*cs++ = 0;
+
+//ALANPREVIN flush + store dword for debug only
+ *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | 3;
+ *cs++ = lower_32_bits(batch_offset + pkt->bb_flush_dword_addr);
+ *cs++ = upper_32_bits(batch_offset + pkt->bb_flush_dword_addr);
+ *cs++ = lower_32_bits(pkt->bb_flush_dword_val);
+ *cs++ = upper_32_bits(pkt->bb_flush_dword_val);
+
*cs++ = MI_BATCH_BUFFER_END;
}
+//ALANPREVIN below helper for debug only
+static void
+check_heci_cmd_complete_nonpriv(struct intel_gsc_uc *gsc, struct intel_gsc_heci_non_priv_pkt *pkt)
+{
+ struct drm_i915_private *i915 = gsc_uc_to_gt(gsc)->i915;
+
+ u64 *ptr64 = pkt->bb_vaddr + pkt->bb_flush_dword_addr;
+
+ if (pkt->bb_vaddr && *ptr64 != pkt->bb_flush_dword_val) {
+ drm_err(&i915->drm, "heci-pkt completion tag = 0x%016llx (expected = 0x%016llx)\n",
+ *ptr64, pkt->bb_flush_dword_val);
+ }
+}
+
int
intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
struct intel_context *ce,
@@ -75,13 +95,17 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
{
struct intel_engine_cs *eng;
struct i915_request *rq;
- int err;
+ u64 batch_gfxoffset;
+ int err = 0;
rq = intel_context_create_request(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
- emit_gsc_heci_pkt_nonpriv(cs, pkt);
+ batch_gfxoffset = i915_vma_offset(pkt->bb_vma);
+ pkt->bb_flush_dword_addr = 2048;
+ pkt->bb_flush_dword_val = 0xFF11DD33AA889944;
+ emit_gsc_heci_pkt_nonpriv(cs, pkt, batch_gfxoffset);
i915_vma_lock(pkt->bb_vma);
err = i915_vma_move_to_active(pkt->bb_vma, rq, EXEC_OBJECT_WRITE);
@@ -98,7 +122,7 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
err = eng->emit_init_breadcrumb(rq);
if (!err)
- err = eng->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0);
+ err = eng->emit_bb_start(rq, batch_gfxoffset, PAGE_SIZE, 0);
if (err) {
i915_request_add(rq);
@@ -116,6 +140,8 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
i915_request_put(rq);
+ check_heci_cmd_complete_nonpriv(gsc, pkt);
+
err = ce->engine->emit_flush(rq, 0);
if (err)
drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
index 394d9929529a..bf82b6f38861 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
@@ -58,6 +58,12 @@ struct intel_gsc_heci_non_priv_pkt {
u32 size_out;
struct i915_vma *heci_pkt_vma;
struct i915_vma *bb_vma;
+
+ //ALANPREVIN - below for debug only
+ u64 bb_flush_dword_addr;
+ u64 bb_flush_dword_val;
+ void *heci_pkt_vaddr;
+ void *bb_vaddr;
};
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 534b0aa43316..915a52ccfd00 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -26,6 +26,7 @@ int intel_huc_fw_load_and_auth_via_gsc(struct intel_huc *huc)
* mark the HuC as loaded.
*/
if (intel_huc_is_authenticated(huc)) {
+ drm_info(&huc_to_gt(huc)->i915->drm, "ALANPREVIN already authenticated HUC\n");
intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
return 0;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 90e739345924..221fd4f85f07 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -10,6 +10,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
+#include <drm/drm_print.h>
#include "intel_pxp.h"
#include "intel_pxp_gsccs.h"
@@ -134,15 +135,24 @@ static void pxp_init_full(struct intel_pxp *pxp)
* so we start it as completed and we reinit it when a termination
* is triggered.
*/
+
+ DRM_INFO("ALANPREVIN INIT-FULL 1\n");
init_completion(&pxp->termination);
complete_all(&pxp->termination);
+ DRM_INFO("ALANPREVIN INIT-FULL 2\n");
+
intel_pxp_session_management_init(pxp);
+ DRM_INFO("ALANPREVIN INIT-FULL 3\n");
+
ret = create_vcs_context(pxp);
if (ret)
return;
+ DRM_INFO("ALANPREVIN INIT-FULL 4 - uses-gsccs = %s\n",
+ pxp->uses_gsccs ? "true" : "false");
+
if (pxp->uses_gsccs) {
ret = intel_pxp_gsccs_init(pxp);
intel_pxp_init_hw(pxp, true);
@@ -152,11 +162,14 @@ static void pxp_init_full(struct intel_pxp *pxp)
if (ret)
goto out_context;
+ DRM_INFO("ALANPREVIN INIT-FULL 5\n");
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return;
out_context:
+ DRM_INFO("ALANPREVIN INIT ERR1\n");
destroy_vcs_context(pxp);
}
@@ -210,6 +223,7 @@ int intel_pxp_init(struct drm_i915_private *i915)
* NOTE: Get the ctrl_gt before checking intel_pxp_is_supported since
* we still need it if PXP's backend tee transport is needed.
*/
+ DRM_INFO("ALANPREVIN INIT 1\n");
gt = find_gt_for_required_protected_content(i915);
if (gt)
is_full_feature = true;
@@ -219,6 +233,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
if (!gt)
return -ENODEV;
+ DRM_INFO("ALANPREVIN INIT 2\n");
+
/*
* At this point, we will either enable full featured PXP capabilities
* including session and object management, or we will init the backend tee
@@ -228,9 +244,16 @@ int intel_pxp_init(struct drm_i915_private *i915)
if (!i915->pxp)
return -ENOMEM;
+ DRM_INFO("ALANPREVIN INIT 3\n");
+
i915->pxp->ctrl_gt = gt;
i915->pxp->uses_gsccs = pxp_has_gsccs(i915);
+ DRM_INFO("ALANPREVIN INIT 4 - uses-gsccs = %s | full-feature = %s\n",
+ str_yes_no(i915->pxp->uses_gsccs), str_yes_no(is_full_feature));
+
+ DRM_INFO("ALANPREVIN INIT 5\n");
+
/*
* If full PXP feature is not available but HuC is loaded by GSC on pre-MTL
* such as DG2, we can skip the init of the full PXP session/object management
@@ -241,14 +264,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
else
intel_pxp_tee_component_init(i915->pxp);
+ DRM_INFO("ALANPREVIN INIT 7\n");
+
return 0;
}
void intel_pxp_fini(struct drm_i915_private *i915)
{
+ DRM_INFO("ALANPREVIN FINI 1\n");
if (!i915->pxp)
return;
+ DRM_INFO("ALANPREVIN FINI 2\n");
+
i915->pxp->arb_is_valid = false;
if (i915->pxp->uses_gsccs) {
@@ -258,8 +286,12 @@ void intel_pxp_fini(struct drm_i915_private *i915)
intel_pxp_tee_component_fini(i915->pxp);
}
+ DRM_INFO("ALANPREVIN FINI 4\n");
+
destroy_vcs_context(i915->pxp);
+ DRM_INFO("ALANPREVIN FINI 6\n");
+
kfree(i915->pxp);
i915->pxp = NULL;
}
@@ -305,29 +337,47 @@ int intel_pxp_start(struct intel_pxp *pxp)
{
int ret = 0;
+ DRM_INFO("ALANPREVIN START 1\n");
+
if (!intel_pxp_is_enabled(pxp))
return -ENODEV;
+ DRM_INFO("ALANPREVIN START 2\n");
+
if (!pxp->uses_gsccs)
if (wait_for(pxp_component_bound(pxp), 250))
return -ENXIO;
+ DRM_INFO("ALANPREVIN START 3\n");
+
mutex_lock(&pxp->arb_mutex);
+ DRM_INFO("ALANPREVIN START 4\n");
+
if (pxp->arb_is_valid)
goto unlock;
+ DRM_INFO("ALANPREVIN START 5\n");
+
pxp_queue_termination(pxp);
+ DRM_INFO("ALANPREVIN START 6\n");
+
if (!wait_for_completion_timeout(&pxp->termination,
msecs_to_jiffies(250))) {
ret = -ETIMEDOUT;
+ DRM_INFO("ALANPREVIN START 6 ERR\n");
goto unlock;
}
+ DRM_INFO("ALANPREVIN START 7\n");
+
/* make sure the compiler doesn't optimize the double access */
barrier();
+ if (!pxp->arb_is_valid)
+ DRM_INFO("ALANPREVIN START 7 ERR\n");
+
if (!pxp->arb_is_valid)
ret = -EIO;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
index 9fe30516eced..a4f321537efb 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.c
@@ -3,6 +3,8 @@
* Copyright(c) 2023 Intel Corporation.
*/
+#include <drm/drm_print.h>
+
#include "gem/i915_gem_internal.h"
#include "gt/intel_context.h"
@@ -53,24 +55,34 @@ static int gsccs_send_message(struct intel_pxp *pxp,
struct intel_gsc_heci_non_priv_pkt pkt;
size_t max_msg_size;
u32 reply_size;
- int ret;
+ int ret, numdw, count;
+
+ DRM_INFO("ALANPREVIN GSCCS-SEND 1\n");
if (!intel_uc_uses_gsc_uc(>->uc))
return -ENODEV;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 2\n");
+
if (!exec->ce)
return -ENODEV;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 3\n");
+
max_msg_size = PXP43_MAX_HECI_IN_SIZE - sizeof(*header);
if (msg_in_size > max_msg_size || msg_out_size_max > max_msg_size)
return -ENOSPC;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 4\n");
+
mutex_lock(&exec->cmd_mutex);
if (!exec->pkt_vma || !exec->bb_vma)
return -ENOENT;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 5-heci-header\n");
+
memset(header, 0, sizeof(*header));
intel_gsc_uc_heci_cmd_emit_mtl_header(header, MTL_HECI_CLIENT_PXP, msg_in_size,
exec->host_session_handle, 0);
@@ -78,6 +90,8 @@ static int gsccs_send_message(struct intel_pxp *pxp,
/* copy caller provided gsc message handle if this is polling for a prior msg completion */
header->gsc_message_handle = *gsc_msg_handle_retry;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 6\n");
+
memcpy(exec->pkt_vaddr + sizeof(*header), msg_in, msg_in_size);
pkt.addr_in = i915_vma_offset(exec->pkt_vma);
@@ -86,6 +100,23 @@ static int gsccs_send_message(struct intel_pxp *pxp,
pkt.size_out = msg_out_size_max + sizeof(*header);
pkt.heci_pkt_vma = exec->pkt_vma;
pkt.bb_vma = exec->bb_vma;
+ pkt.bb_vaddr = exec->bb_vaddr;
+
+ DRM_INFO("ALANPREVIN GSCCS-SEND 7-heci-submit\n");
+
+ /* DUMP IN --------------------- */
+ drm_info(&i915->drm, "ALANPREVIN gsccs send msg IN-dwords:\n");
+ numdw = (sizeof(*header) + msg_in_size) / 4;
+ if (numdw > 30) {
+ drm_info(&i915->drm, "(clipp dwords from %ld)\n", (msg_in_size / 4));
+ numdw = 30;
+ }
+ for (count = 0; count < numdw; ++count) {
+ u32 tmp = *((u32 *)(exec->pkt_vaddr + count * 4));
+
+ drm_info(&i915->drm, " ALANPREVIN INDW-%d : 0x%08x\n",
+ count, tmp);
+ }
ret = intel_gsc_uc_heci_cmd_submit_nonpriv(&pxp->ctrl_gt->uc.gsc,
exec->ce, &pkt, exec->bb_vaddr, 500);
@@ -95,8 +126,24 @@ static int gsccs_send_message(struct intel_pxp *pxp,
}
/* we keep separate location for reply, so go to the response header now */
+ /* DUMP OUT --------------------- */
+ drm_info(&i915->drm, "ALANPREVIN gsccs send msg OUT-dwords:\n");
+ numdw = msg_out_size_max / 4;
+ if (numdw > 30) {
+ drm_info(&i915->drm, "(clipp dwords from %ld)\n", (msg_out_size_max / 4));
+ numdw = 30;
+ }
+ for (count = 0; count < numdw; ++count) {
+ u32 tmp = *((u32 *)(exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE + count * 4));
+
+ drm_info(&i915->drm, " ALANPREVIN OUTDW-%d : 0x%08x\n",
+ count, tmp);
+ }
+
header = exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 8\n");
+
/* Response validity marker, status and busyness */
if (header->validity_marker != MTL_HECI_VALIDITY_MARKER) {
drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n");
@@ -122,6 +169,8 @@ static int gsccs_send_message(struct intel_pxp *pxp,
goto unlock;
}
+ DRM_INFO("ALANPREVIN GSCCS-SEND 9\n");
+
reply_size = header->message_size - sizeof(*header);
if (reply_size > msg_out_size_max) {
drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%ld)\n",
@@ -132,11 +181,15 @@ static int gsccs_send_message(struct intel_pxp *pxp,
reply_size, msg_out_size_max);
}
+ DRM_INFO("ALANPREVIN GSCCS-SEND 10\n");
+
memcpy(msg_out, exec->pkt_vaddr + PXP43_MAX_HECI_IN_SIZE + sizeof(*header),
reply_size);
if (msg_out_len)
*msg_out_len = reply_size;
+ DRM_INFO("ALANPREVIN GSCCS-SEND 11\n");
+
unlock:
mutex_unlock(&exec->cmd_mutex);
return ret;
@@ -152,9 +205,13 @@ int intel_pxp_gsccs_create_session(struct intel_pxp *pxp,
int insize, outsize, ret, tries = 0;
void *inptr, *outptr;
+ DRM_INFO("ALANPREVIN GSCCS-ARB-CREATE 0\n");
+
/* get a unique host-session-handle (used later in HW cmds) at time of session creation */
get_random_bytes(&exec->host_session_handle, sizeof(exec->host_session_handle));
+ DRM_INFO("ALANPREVIN GSCCS-ARB-CREATE 1\n");
+
msg_in.header.api_version = PXP_APIVER(4, 3);
msg_in.header.command_id = PXP43_CMDID_INIT_SESSION;
msg_in.header.stream_id = (FIELD_PREP(PXP43_INIT_SESSION_APPID, arb_session_id) |
@@ -163,6 +220,8 @@ int intel_pxp_gsccs_create_session(struct intel_pxp *pxp,
msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
msg_in.protection_mode = PXP43_INIT_SESSION_PROTECTION_ARB;
+ DRM_INFO("ALANPREVIN GSCCS-ARB-CREATE 2\n");
+
inptr = &msg_in;
outptr = &msg_out;
insize = sizeof(msg_in);
@@ -211,6 +270,8 @@ gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname,
{
int err = 0;
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 1 for %s\n", bufname);
+
*obj = i915_gem_object_create_internal(i915, size);
if (IS_ERR(*obj)) {
drm_err(&i915->drm, "Failed to allocate gsccs backend %s.\n", bufname);
@@ -218,6 +279,8 @@ gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname,
goto out_none;
}
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 2 for %s\n", bufname);
+
*vma = i915_vma_instance(*obj, &ppgtt->vm, NULL);
if (IS_ERR(*vma)) {
drm_err(&i915->drm, "Failed to vma-instance gsccs backend %s.\n", bufname);
@@ -225,12 +288,16 @@ gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname,
goto out_put;
}
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 3 for %s\n", bufname);
+
err = i915_gem_object_pin_pages_unlocked(*obj);
if (err) {
drm_err(&i915->drm, "Failed to pin gsccs backend %s.\n", bufname);
goto out_put;
}
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 4 for %s\n", bufname);
+
/* map to the virtual memory pointer */
*map = i915_gem_object_pin_map_unlocked(*obj, i915_coherent_map_type(i915, *obj, true));
if (IS_ERR(*map)) {
@@ -239,6 +306,8 @@ gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname,
goto out_unpin;
}
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 5 for %s\n", bufname);
+
/* all PXP sessions commands are treated as non-priveleged */
err = i915_vma_pin(*vma, 0, 0, PIN_USER);
if (err) {
@@ -246,6 +315,8 @@ gsccs_create_buffer(struct drm_i915_private *i915, const char *bufname,
goto out_unmap;
}
+ DRM_INFO("ALANPREVIN GSCCS-BUF-CREATE 6 for %s\n", bufname);
+
return 0;
out_unmap:
@@ -288,6 +359,8 @@ gsccs_allocate_execution_resource(struct intel_pxp *pxp,
struct intel_context *ce;
int err = 0;
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 1\n");
+
/*
* First, ensure the GSC engine is present.
* NOTE: Backend should would only be called with the correct gt.
@@ -295,12 +368,16 @@ gsccs_allocate_execution_resource(struct intel_pxp *pxp,
if (!engine)
return -ENODEV;
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 2\n");
+
mutex_init(&strm_res->cmd_mutex);
ppgtt = i915_ppgtt_create(gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 3\n");
+
strm_res->ppgtt = ppgtt;
/*
@@ -318,6 +395,8 @@ gsccs_allocate_execution_resource(struct intel_pxp *pxp,
return err;
}
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 4\n");
+
err = gsccs_create_buffer(pxp->ctrl_gt->i915, "Batch Buffer",
PAGE_SIZE, strm_res->ppgtt,
&strm_res->bb_obj, &strm_res->bb_vma,
@@ -326,6 +405,9 @@ gsccs_allocate_execution_resource(struct intel_pxp *pxp,
gsccs_destroy_execution_resource(pxp, strm_res);
return err;
}
+
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 5\n");
+
/*
* TODO: Consider optimization of pre-populating batch buffer
* with the send-HECI instruction now at init and reuse through its life.
@@ -338,11 +420,16 @@ gsccs_allocate_execution_resource(struct intel_pxp *pxp,
gsccs_destroy_execution_resource(pxp, strm_res);
return PTR_ERR(ce);
}
+
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 6\n");
+
i915_vm_put(ce->vm);
ce->vm = i915_vm_get(&ppgtt->vm);
strm_res->ce = ce;
+ DRM_INFO("ALANPREVIN GSCCS-EXEC-ALLOC 7\n");
+
return 0;
}
@@ -363,16 +450,22 @@ int intel_pxp_gsccs_init(struct intel_pxp *pxp)
struct gsccs_teelink_priv *gsccs;
int ret;
+ DRM_INFO("ALANPREVIN GSCCS-INIT 1\n");
+
gsccs = kzalloc(sizeof(*gsccs), GFP_KERNEL);
if (!gsccs)
return -ENOMEM;
+ DRM_INFO("ALANPREVIN GSCCS-INIT 2\n");
+
ret = gsccs_allocate_execution_resource(pxp, &gsccs->arb_exec_res);
if (ret) {
kfree(gsccs);
return ret;
}
+ DRM_INFO("ALANPREVIN GSCCS-INIT 4\n");
+
pxp->gsccs_priv = gsccs;
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 2eef0c19e91a..6df7521512e1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -48,6 +48,8 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
gt = intel_pxp_get_irq_gt(pxp);
+ DRM_INFO("ALANPREVIN - PXP-IRQ-HANDLER 1");
+
lockdep_assert_held(gt->irq_lock);
if (unlikely(!iir))
@@ -56,6 +58,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
if (iir & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT |
GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT)) {
/* immediately mark PXP as inactive on termination */
+ DRM_INFO("ALANPREVIN - PXP-IRQ-HANDLER -TERM!");
intel_pxp_mark_termination_in_progress(pxp);
pxp->session_events |= PXP_TERMINATION_REQUEST | PXP_INVAL_REQUIRED;
}
@@ -63,6 +66,9 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
pxp->session_events |= PXP_TERMINATION_COMPLETE;
+ if (iir & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
+ DRM_INFO("ALANPREVIN - PXP-IRQ-HANDLER -CMPLT!");
+
if (pxp->session_events)
queue_work(system_unbound_wq, &pxp->session_work);
}
@@ -92,6 +98,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
+ DRM_INFO("ALANPREVIN - PXP-IRQ-ON!");
__pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
pxp->irq_enabled = true;
@@ -114,6 +121,7 @@ void intel_pxp_irq_disable(struct intel_pxp *pxp)
spin_lock_irq(gt->irq_lock);
pxp->irq_enabled = false;
+ DRM_INFO("ALANPREVIN - PXP-IRQ-OFF!");
__pxp_set_interrupts(gt, 0);
spin_unlock_irq(gt->irq_lock);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index e4e60e3b9216..68ea613723b5 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -70,11 +70,15 @@ static int pxp_create_arb_session(struct intel_pxp *pxp)
pxp->arb_is_valid = false;
+ DRM_INFO("ALANPREVIN CREATE ARB 1\n");
+
if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) {
drm_err(>->i915->drm, "arb session already in play at creation time\n");
return -EEXIST;
}
+ DRM_INFO("ALANPREVIN CREATE ARB 2\n");
+
if (pxp->uses_gsccs)
ret = intel_pxp_gsccs_create_session(pxp, ARB_SESSION);
else
@@ -84,6 +88,8 @@ static int pxp_create_arb_session(struct intel_pxp *pxp)
return ret;
}
+ DRM_INFO("ALANPREVIN CREATE ARB 3\n");
+
ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true);
if (ret) {
drm_err(>->i915->drm, "arb session failed to go in play\n");
@@ -104,6 +110,8 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
int ret;
struct intel_gt *gt = pxp->ctrl_gt;
+ DRM_INFO("ALANPREVIN TERMINATE GLOBAL 1\n");
+
/* must mark termination in progress calling this function */
GEM_WARN_ON(pxp->arb_is_valid);
@@ -114,17 +122,23 @@ static int pxp_terminate_arb_session_and_global(struct intel_pxp *pxp)
return ret;
}
+ DRM_INFO("ALANPREVIN TERMINATE GLOBAL 2\n");
+
ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
if (ret) {
drm_err(>->i915->drm, "Session state did not clear\n");
return ret;
}
+ DRM_INFO("ALANPREVIN TERMINATE GLOBAL 3\n");
+
if (pxp->gsccs_priv)
intel_uncore_write(gt->uncore, MTL_KCR_GLOBAL_TERMINATE, 1);
else
intel_uncore_write(gt->uncore, GEN12_KCR_GLOBAL_TERMINATE, 1);
+ DRM_INFO("ALANPREVIN TERMINATE GLOBAL 4\n");
+
return ret;
}
--
2.39.0
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