[PATCH] drm/i915/display: Add some more debug into psr code

[Jouni Högander]

Add some debug into selective fetch area calculation and psr2 state
control.

Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7d4a15a283a0..43e900f5580d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1099,6 +1099,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	else
 		hsw_activate_psr1(intel_dp);
 
+	drm_dbg_kms(&dev_priv->drm, "PSR activated\n");
 	intel_dp->psr.active = true;
 }
 
@@ -1320,7 +1321,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		intel_de_write(dev_priv,
 			       EDP_PSR_CTL(intel_dp->psr.transcoder), val);
 	}
+
 	intel_dp->psr.active = false;
+
+	drm_dbg_kms(&dev_priv->drm, "PSR exited\n");
 }
 
 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
@@ -1447,6 +1451,8 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	if (!CAN_PSR(intel_dp))
 		return;
 
+	drm_dbg_kms(&dev_priv->drm, "PSR about to be paused\n");
+
 	mutex_lock(&psr->lock);
 
 	if (!psr->enabled) {
@@ -1475,11 +1481,14 @@ void intel_psr_pause(struct intel_dp *intel_dp)
  */
 void intel_psr_resume(struct intel_dp *intel_dp)
 {
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_psr *psr = &intel_dp->psr;
 
 	if (!CAN_PSR(intel_dp))
 		return;
 
+	drm_dbg_kms(&dev_priv->drm, "PSR about to be resumed\n");
+
 	mutex_lock(&psr->lock);
 
 	if (!psr->paused)
@@ -1523,13 +1532,15 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	if (intel_dp->psr.psr2_sel_fetch_enabled)
+	if (intel_dp->psr.psr2_sel_fetch_enabled) {
+		drm_dbg_kms(&dev_priv->drm, "Setting SFF bit\n");
 		intel_de_write(dev_priv,
 			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
 			       man_trk_ctl_enable_bit_get(dev_priv) |
 			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
 			       man_trk_ctl_single_full_frame_bit_get(dev_priv) |
 			       man_trk_ctl_continuos_full_frame(dev_priv));
+	}
 
 	/*
 	 * Display WA #0884: skl+
@@ -1544,6 +1555,8 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 	 * but testing proved that it works for up display 13, for newer
 	 * than that testing will be needed.
 	 */
+	drm_dbg_kms(&dev_priv->drm, "Sending update frame\n");
+
 	intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
 }
 
@@ -1556,6 +1569,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
 	if (!crtc_state->enable_psr2_sel_fetch)
 		return;
 
+	drm_dbg_kms(&dev_priv->drm, "Disabling sel fetch for plane = %d\n", plane->id);
 	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
 }
 
@@ -1574,6 +1588,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 		return;
 
 	if (plane->id == PLANE_CURSOR) {
+		drm_dbg_kms(&dev_priv->drm, "Enabling cursor plane sel fetch\n");
 		intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
 				  plane_state->ctl);
 		return;
@@ -1581,6 +1596,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 
 	clip = &plane_state->psr2_sel_fetch_area;
 
+	drm_dbg_kms(&dev_priv->drm, "Programming sel fetch area for plane id %d (%d,%d)\n", plane->id, clip->y1, clip->y2);
+
 	val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
 	val |= plane_state->uapi.dst.x1;
 	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
@@ -1628,6 +1645,9 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 		break;
 	}
 
+	drm_dbg_kms(&dev_priv->drm, "psr2_man_track_ctl = 0x%x\n",
+		    crtc_state->psr2_man_track_ctl);
+
 	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
 		       crtc_state->psr2_man_track_ctl);
 }
@@ -1639,6 +1659,9 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val = man_trk_ctl_enable_bit_get(dev_priv);
 
+	drm_dbg_kms(&dev_priv->drm, "clip->y1 = %d, clip->y2 = %d, full_update = %s\n",
+		    clip->y1, clip->y2, str_yes_no(full_update));
+
 	/* SF partial frame enable has to be set even on full update */
 	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
 
@@ -1833,7 +1856,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	 * calculation for those.
 	 */
 	if (pipe_clip.y1 == -1) {
-		drm_info_once(&dev_priv->drm,
+		drm_dbg_kms(&dev_priv->drm,
 			      "Selective fetch area calculation failed in pipe %c\n",
 			      pipe_name(crtc->pipe));
 		full_update = true;
@@ -2235,6 +2258,7 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp)
 			return;
 		}
 
+		drm_dbg_kms(&dev_priv->drm, "Setting cff bit\n");
 		val = man_trk_ctl_enable_bit_get(dev_priv) |
 		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
 		      man_trk_ctl_continuos_full_frame(dev_priv);
@@ -2333,6 +2357,7 @@ static void _psr_flush_handle(struct intel_dp *intel_dp)
 				 * SU configuration in case update is sent for any reason after
 				 * sff bit gets cleared by the HW on next vblank.
 				 */
+				drm_dbg_kms(&dev_priv->drm, "Disabling CFF\n");
 				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
 					       val);
 				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
-- 
2.34.1