[PATCH 3/5] drm/i915/vdsc: Add function to write in PPS registers
Suraj Kandpal
suraj.kandpal at intel.com
Fri Jul 7 10:20:42 UTC 2023
Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.
Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 494 +++++++++++-----------
1 file changed, 252 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 53eac8d9c80f..274d82360c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -310,6 +310,244 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
}
+static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
+ enum intel_dsc_pps pps, u32 pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ switch (pps) {
+ case PPS_0:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_0,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_0,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_1:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_1,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_1,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_2:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_2,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_2,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_3:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_3,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_3,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_4:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_4,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_4,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_5:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_5,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_5,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_6:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_6,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_6,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_7:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_7,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_7,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_8:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_8,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_8,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_9:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_9,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_9,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_10:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_10,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_10,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
+ pps_val);
+ }
+ break;
+ case PPS_16:
+ if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(i915, DSCA_PICTURE_PARAMETER_SET_16,
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915, DSCC_PICTURE_PARAMETER_SET_16,
+ pps_val);
+ } else {
+ intel_de_write(i915,
+ ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
+ pps_val);
+ }
+ break;
+ /* Since PPS_17 and PPS_18 were introduced from MTL dsc check need not be done */
+ case PPS_17:
+ intel_de_write(i915,
+ MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+ pps_val);
+ break;
+ case PPS_18:
+ intel_de_write(i915,
+ MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(i915,
+ MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+ pps_val);
+ break;
+ default:
+ drm_err(&i915->drm, "PPS register does not exist\n");
+ break;
+ }
+}
+
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -347,149 +585,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_VBR_ENABLE;
drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_0, pps_val);
/* Populate PICTURE_PARAMETER_SET_1 registers */
pps_val = 0;
pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_1, pps_val);
/* Populate PICTURE_PARAMETER_SET_2 registers */
pps_val = 0;
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_2, pps_val);
/* Populate PICTURE_PARAMETER_SET_3 registers */
pps_val = 0;
pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_3, pps_val);
/* Populate PICTURE_PARAMETER_SET_4 registers */
pps_val = 0;
pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_4, pps_val);
/* Populate PICTURE_PARAMETER_SET_5 registers */
pps_val = 0;
pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_5, pps_val);
/* Populate PICTURE_PARAMETER_SET_6 registers */
pps_val = 0;
@@ -498,100 +628,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_6, pps_val);
/* Populate PICTURE_PARAMETER_SET_7 registers */
pps_val = 0;
pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_7, pps_val);
/* Populate PICTURE_PARAMETER_SET_8 registers */
pps_val = 0;
pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_8, pps_val);
/* Populate PICTURE_PARAMETER_SET_9 registers */
pps_val = 0;
pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_9, pps_val);
/* Populate PICTURE_PARAMETER_SET_10 registers */
pps_val = 0;
@@ -600,25 +658,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- DSCC_PICTURE_PARAMETER_SET_10, pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_10, pps_val);
/* Populate Picture parameter set 16 */
pps_val = 0;
@@ -628,51 +668,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
- pps_val);
- /*
- * If 2 VDSC instances are needed, configure PPS for second
- * VDSC
- */
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- DSCC_PICTURE_PARAMETER_SET_16, pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, PPS_16, pps_val);
if (DISPLAY_VER(dev_priv) >= 14) {
/* Populate PICTURE_PARAMETER_SET_17 registers */
pps_val = 0;
pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
- intel_de_write(dev_priv,
- MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
- pps_val);
+ intel_dsc_write_pps_reg(crtc_state, PPS_17, pps_val);
/* Populate PICTURE_PARAMETER_SET_18 registers */
pps_val = 0;
pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
- intel_de_write(dev_priv,
- MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
- pps_val);
- if (crtc_state->dsc.dsc_split)
- intel_de_write(dev_priv,
- MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
- pps_val);
+ intel_dsc_write_pps_reg(crtc_state, PPS_18, pps_val);
}
/* Populate the RC_BUF_THRESH registers */
--
2.25.1
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