[PATCH 10/10] clear up cs stuff

[Andi Shyti]

---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 4fab07de1ab4a..c2cde3e83870b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -199,6 +199,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
 	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
 	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
 	*cs++ = AUX_INV;
+	*cs++ = MI_NOOP;
 
 	*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
 		MI_SEMAPHORE_REGISTER_POLL |
@@ -208,6 +209,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
 	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
 	*cs++ = 0;
 	*cs++ = 0;
+	*cs++ = MI_NOOP;
 
 	return cs;
 }
@@ -324,7 +326,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 
 		count = 8;
 		if (HAS_AUX_CCS(rq->engine->i915))
-			count += 8;
+			count += 10;
 
 		cs = intel_ring_begin(rq, count);
 		if (IS_ERR(cs))
@@ -365,7 +367,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 		u32 bit_group_0 = 0;
 		u32 bit_group_1 = 0;
 
-		cmd += 8;
+		cmd += 10;
 
 		bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
 
@@ -391,13 +393,13 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 
 		case VIDEO_ENHANCEMENT_CLASS:
 		case COMPUTE_CLASS:
-			cmd += 2;
+			//cmd += 2;
 			cmd_flush = MI_FLUSH_DW;
 
 			break;
 
 		case COPY_ENGINE_CLASS:
-			cmd += 2;
+			//cmd += 2;
 			/*
 			 * When required, in MTL+ platforms we need to
 			 * set the CCS_FLUSH bit in the pipe control
@@ -411,10 +413,12 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
+	/*
 	if (cmd_flush) {
 		*cs++ = cmd_flush;
 		*cs++ = 0;
 	}
+	*/
 
 	if (mode & EMIT_INVALIDATE)
 		*cs++ = preparser_disable(true);
-- 
2.40.1