[PATCH 1/2] drm/i915: Skip clflush after GPU access on snooping platforms

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

On snooping platforms CPU cache will not contain stale data after GPU
access since write-invalidate protocol is used, which means there is
no need to flush before potentially transitioning the buffer to a
non-coherent domain.

Use the opportunity to documet the situation on discrete too.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Cc: Matt Roper <matthew.d.roper at intel.com>
Cc: Fei Yang <fei.yang at intel.com>
Cc: Matthew Auld <matthew.auld at intel.com>
Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index ffddec1d2a76..1f02b30e3759 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -24,9 +24,19 @@ static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
 
+	/*
+	 * Discrete GPUs can not cache in the CPU cache.
+	 */
 	if (IS_DGFX(i915))
 		return false;
 
+	/*
+	 * Integrated GPUs with snooping are using write-invalidate so GPU
+	 * writes will not end up in the CPU cache.
+	 */
+	if (!HAS_LLC(i915) && HAS_SNOOP(i915))
+		return false;
+
 	/*
 	 * For objects created by userspace through GEM_CREATE with pat_index
 	 * set by set_pat extension, i915_gem_object_has_cache_level() will
-- 
2.39.2