[PATCH] drm/i915/psr: Instrument io/fast wake line configuration

[Jouni Högander]

Printout calculated io/fast wake lines and the actual value
written into PSR2 CTL register.

Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d58ed9b62e67..03510f032750 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -638,6 +638,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 	}
 
+	drm_dbg_kms(&dev_priv->drm, "Calculated io wake lines = %d\n",
+		    intel_dp->psr.io_wake_lines);
+	drm_dbg_kms(&dev_priv->drm, "Calculated fast wake lines = %d\n",
+		    intel_dp->psr.fast_wake_lines);
+
 	/* Wa_22012278275:adl-p */
 	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 		static const u8 map[] = {
@@ -687,6 +692,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	 */
 	intel_de_write(dev_priv, EDP_PSR_CTL(cpu_transcoder), 0);
 
+	drm_dbg_kms(&dev_priv->drm, "EDP_PSR2_CTL = 0x%x\n",
+		    val);
+
 	intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);
 }
 
@@ -948,6 +956,11 @@ static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
 	intel_dp->psr.io_wake_lines = max(io_wake_lines, 7);
 	intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7);
 
+	drm_dbg_kms(&i915->drm, "Calculated io wake lines = %d\n",
+		    intel_dp->psr.io_wake_lines);
+	drm_dbg_kms(&i915->drm, "Calculated fast wake lines = %d\n",
+		    intel_dp->psr.fast_wake_lines);
+
 	return true;
 }
 
-- 
2.34.1