[RFC PATCH 14/22] drm/i915/psr: Remove invalidate callback
Jouni Högander
jouni.hogander at intel.com
Fri Mar 24 11:24:57 UTC 2023
We do not have frontbuffer tracking invalidate interface anymore.
Remove psr invalidate callback.
Cff workaround can be removed as it's relying invalidate/flush
pairs. Now the strategy is to send one full update when frontbuffer
rendering is complete and dirtyfb ioctl is made.
Earlier PSR1 was exited on invalidate and re-activated on flush. Now
as we have only flush we can remove this code as well.
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_psr.c | 172 +-----------------
drivers/gpu/drm/i915/display/intel_psr.h | 3 -
3 files changed, 5 insertions(+), 171 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a9060b5b894c..0f30942e6931 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1621,7 +1621,6 @@ struct intel_psr {
bool colorimetry_support;
bool psr2_enabled;
bool psr2_sel_fetch_enabled;
- bool psr2_sel_fetch_cff_enabled;
bool req_psr2_sdp_prior_scanline;
u8 sink_sync_latency;
u8 io_wake_lines;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 42122536f2a8..6cf4d5d19d89 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1264,7 +1264,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
intel_dp->psr.dc3co_exit_delay = val;
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
- intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
intel_dp->psr.req_psr2_sdp_prior_scanline =
crtc_state->req_psr2_sdp_prior_scanline;
@@ -1389,7 +1388,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
intel_dp->psr.enabled = false;
intel_dp->psr.psr2_enabled = false;
intel_dp->psr.psr2_sel_fetch_enabled = false;
- intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
}
/**
@@ -1611,21 +1609,10 @@ void intel_psr2_program_plane_sel_fetch_noarm(struct intel_plane *plane,
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_encoder *encoder;
if (!crtc_state->enable_psr2_sel_fetch)
return;
- for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
- crtc_state->uapi.encoder_mask) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- lockdep_assert_held(&intel_dp->psr.lock);
- if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
- return;
- break;
- }
-
intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
crtc_state->psr2_man_track_ctl);
}
@@ -2055,36 +2042,6 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat
}
}
-static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- i915_reg_t reg;
- u32 mask;
- int err;
-
- if (!intel_dp->psr.enabled)
- return false;
-
- if (intel_dp->psr.psr2_enabled) {
- reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
- mask = EDP_PSR2_STATUS_STATE_MASK;
- } else {
- reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
- mask = EDP_PSR_STATUS_STATE_MASK;
- }
-
- mutex_unlock(&intel_dp->psr.lock);
-
- err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
- if (err)
- drm_err(&dev_priv->drm,
- "Timed out waiting for PSR Idle for re-enable\n");
-
- /* After the unlocked wait, verify that PSR is still wanted! */
- mutex_lock(&intel_dp->psr.lock);
- return err == 0 && intel_dp->psr.enabled;
-}
-
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
{
struct drm_connector_list_iter conn_iter;
@@ -2205,93 +2162,10 @@ static void intel_psr_work(struct work_struct *work)
if (READ_ONCE(intel_dp->psr.irq_aux_error))
intel_psr_handle_irq(intel_dp);
- /*
- * We have to make sure PSR is ready for re-enable
- * otherwise it keeps disabled until next full enable/disable cycle.
- * PSR might take some time to get fully disabled
- * and be ready for re-enable.
- */
- if (!__psr_wait_for_idle_locked(intel_dp))
- goto unlock;
-
- /*
- * The delayed work can race with an invalidate hence we need to
- * recheck. Since psr_flush first clears this and then reschedules we
- * won't ever miss a flush when bailing out here.
- */
- if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
- goto unlock;
-
- intel_psr_activate(intel_dp);
unlock:
mutex_unlock(&intel_dp->psr.lock);
}
-static void _psr_invalidate_handle(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (intel_dp->psr.psr2_sel_fetch_enabled) {
- u32 val;
-
- if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
- /* Send one update otherwise lag is observed in screen */
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
- return;
- }
-
- val = man_trk_ctl_enable_bit_get(dev_priv) |
- man_trk_ctl_partial_frame_bit_get(dev_priv) |
- man_trk_ctl_continuos_full_frame(dev_priv);
- intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
- intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
- } else {
- intel_psr_exit(intel_dp);
- }
-}
-
-/**
- * intel_psr_invalidate - Invalidate PSR
- * @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
- * @origin: which operation caused the invalidate
- *
- * Since the hardware frontbuffer tracking has gaps we need to integrate
- * with the software frontbuffer tracking. This function gets called every
- * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
- * disabled if the frontbuffer mask contains a buffer relevant to PSR.
- *
- * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
- */
-void intel_psr_invalidate(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits, enum fb_op_origin origin)
-{
- struct intel_encoder *encoder;
-
- if (origin == ORIGIN_FLIP)
- return;
-
- for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
- mutex_lock(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled) {
- mutex_unlock(&intel_dp->psr.lock);
- continue;
- }
-
- pipe_frontbuffer_bits &=
- INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
- intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
-
- if (pipe_frontbuffer_bits)
- _psr_invalidate_handle(intel_dp);
-
- mutex_unlock(&intel_dp->psr.lock);
- }
-}
/*
* When we will be completely rely on PSR2 S/W tracking in future,
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
@@ -2319,45 +2193,6 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
intel_dp->psr.dc3co_exit_delay);
}
-static void _psr_flush_handle(struct intel_dp *intel_dp)
-{
- struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-
- if (intel_dp->psr.psr2_sel_fetch_enabled) {
- if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
- /* can we turn CFF off? */
- if (intel_dp->psr.busy_frontbuffer_bits == 0) {
- u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
- man_trk_ctl_partial_frame_bit_get(dev_priv) |
- man_trk_ctl_single_full_frame_bit_get(dev_priv) |
- man_trk_ctl_continuos_full_frame(dev_priv);
-
- /*
- * Set psr2_sel_fetch_cff_enabled as false to allow selective
- * updates. Still keep cff bit enabled as we don't have proper
- * SU configuration in case update is sent for any reason after
- * sff bit gets cleared by the HW on next vblank.
- */
- intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
- val);
- intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
- intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
- }
- } else {
- /*
- * continuous full frame is disabled, only a single full
- * frame is required
- */
- psr_force_hw_tracking_exit(intel_dp);
- }
- } else {
- psr_force_hw_tracking_exit(intel_dp);
-
- if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
- schedule_work(&intel_dp->psr.work);
- }
-}
-
/**
* intel_psr_flush - Flush PSR
* @dev_priv: i915 device
@@ -2408,8 +2243,11 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
if (pipe_frontbuffer_bits == 0)
goto unlock;
- /* By definition flush = invalidate + flush */
- _psr_flush_handle(intel_dp);
+ psr_force_hw_tracking_exit(intel_dp);
+
+ if (intel_dp->psr.psr2_sel_fetch_enabled)
+ goto unlock;
+
unlock:
mutex_unlock(&intel_dp->psr.lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..8e76c9b05bf3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -28,9 +28,6 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
-void intel_psr_invalidate(struct drm_i915_private *dev_priv,
- unsigned frontbuffer_bits,
- enum fb_op_origin origin);
void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
--
2.34.1
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